公开(公告)号：US20240273039A1

公开(公告)日：2024-08-15

申请号：US18589259

申请日：2024-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20240257846A1

公开(公告)日：2024-08-01

申请号：US18584434

申请日：2024-02-22

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20240231699A9

公开(公告)日：2024-07-11

申请号：US18497888

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

公开(公告)号：US12032508B2

公开(公告)日：2024-07-09

申请号：US18144349

申请日：2023-05-08

Applicant: Rambus Inc.

Inventor： Yuanlong Wang

IPC: G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/10 ,  Y02D10/00 ,  Y02D30/50

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

公开(公告)号：US20240211420A1

公开(公告)日：2024-06-27

申请号：US18569451

申请日：2022-06-20

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Dongyun LEE

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/1689

Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.

公开(公告)号：US12002540B2

公开(公告)日：2024-06-04

申请号：US18214466

申请日：2023-06-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C29/02 ,  G11C5/02 ,  G11C5/04 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C11/4063 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US20240177747A1

公开(公告)日：2024-05-30

申请号：US18388680

申请日：2023-11-10

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C7/10 ,  G06F12/00 ,  G06F13/16

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20240146336A1

公开(公告)日：2024-05-02

申请号：US18498832

申请日：2023-10-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Alexander Hamburg ,  John Eric Linstadt ,  Evan Lawrence Erickson

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/6312 ,  H03M13/159 ,  H03M13/43

Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

公开(公告)号：US11972121B2

公开(公告)日：2024-04-30

申请号：US17800601

申请日：2021-02-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Liji Gopalakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

公开(公告)号：US20240134574A1

公开(公告)日：2024-04-25

申请号：US18497888

申请日：2023-10-29

Applicant: Rambus Inc.

Inventor： Srinivas Satish Babu Bamdhamravuri

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.