公开(公告)号：US07271497B2

公开(公告)日：2007-09-18

申请号：US10386211

申请日：2003-03-10

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract translation: 公开了一种用于形成螺柱凸起的半导体管芯的方法。 该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。 将形成的球按压到半导体管芯上的导电区域。 涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

公开(公告)号：US20060284291A1

公开(公告)日：2006-12-21

申请号：US11448962

申请日：2006-06-06

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

公开(公告)号：US20060189116A1

公开(公告)日：2006-08-24

申请号：US11404650

申请日：2006-04-14

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie Rios ,  Erwin Victor Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie Rios ,  Erwin Victor Cruz

IPC: H01L21/44

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

公开(公告)号：US20060151861A1

公开(公告)日：2006-07-13

申请号：US11035918

申请日：2005-01-13

Applicant: Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

Inventor： Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC: H01L23/495

CPC classification number: H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US07061077B2

公开(公告)日：2006-06-13

申请号：US10233248

申请日：2002-08-30

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

公开(公告)号：US07022548B2

公开(公告)日：2006-04-04

申请号：US10744849

申请日：2003-12-22

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/48

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2924/013

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract translation: 公开了一种处理半导体衬底的方法。 该方法包括在具有导电区域的半导体衬底上提供具有孔的掩模。 掩模中的孔设置在导电区上。 将预先形成的导电柱放置在孔中并结合到导电区。

公开(公告)号：US20060006550A1

公开(公告)日：2006-01-12

申请号：US11180367

申请日：2005-07-12

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

公开(公告)号：US20050280126A1

公开(公告)日：2005-12-22

申请号：US11213182

申请日：2005-08-25

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

公开(公告)号：US20050218300A1

公开(公告)日：2005-10-06

申请号：US10817195

申请日：2004-04-02

Applicant: Maria Clemens Quinones ,  Rajeev Joshi

Inventor： Maria Clemens Quinones ,  Rajeev Joshi

IPC: A61B5/00 ,  G02B6/42 ,  H01J40/14 ,  H01L31/00

CPC classification number: G02B6/4201 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An optocoupler package is disclosed. The optocoupler package includes a substrate comprising a leadframe and a molding compound, and a plurality of optocouplers, each optocoupler including (i) an optical emitter, (ii) an optical receiver, (iii) and an optically transmissive medium disposed between the optical emitter and optical receiver, where the optical emitter and the optical receiver are electrically coupled to the leadframe.

Abstract translation: 公开了一种光耦合器封装。 光耦合器包括包括引线框架和模制化合物的基板和多个光耦合器，每个光耦合器包括（i）光发射器，（ii）光接收器，（iii）和设置在光发射器 和光接收器，其中光发射器和光接收器电耦合到引线框架。

公开(公告)号：US20050206010A1

公开(公告)日：2005-09-22

申请号：US10803464

申请日：2004-03-18

Applicant: Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。