公开(公告)号：US07541291B2

公开(公告)日：2009-06-02

申请号：US11821422

申请日：2007-06-22

申请人： Sean S. Kang ,  Sangheon Lee ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Gan Ming Zhao

发明人： Sean S. Kang ,  Sangheon Lee ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Gan Ming Zhao

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

摘要： A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

摘要翻译： 提供了一个图层中的一个特征。 在该层上形成光致抗蚀剂层。 光致抗蚀剂层被图案化以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征，其中光致抗蚀剂特征具有第一临界尺寸。 在光致抗蚀剂特征的侧壁上沉积保形层以减少光致抗蚀剂特征的临界尺寸。 将特征蚀刻到层中，其中层特征具有小于第一临界尺寸的第二临界尺寸。

公开(公告)号：US07485581B2

公开(公告)日：2009-02-03

申请号：US11291411

申请日：2005-11-30

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

摘要翻译： 提供一种降低半导体器件之间的电容的方法。 在电介质层中形成多个接触结构。 形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。 掩模特征的宽度随着侧壁沉积而收缩。 间隙通过侧壁沉积蚀刻到介电层中。 间隙封闭以形成间隙中的凹坑。

公开(公告)号：US07476610B2

公开(公告)日：2009-01-13

申请号：US11598242

申请日：2006-11-10

申请人： Ji Soo Kim ,  Conan Chiang ,  Daehan Choi ,  S. M. Reza Sadjadi ,  Michael Goss

发明人： Ji Soo Kim ,  Conan Chiang ,  Daehan Choi ,  S. M. Reza Sadjadi ,  Michael Goss

IPC分类号： H01L21/44

CPC分类号： H01L29/6659 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

摘要翻译： 提供了一种用于形成半导体器件的方法。 栅极堆叠形成在衬底的表面上。 提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相 聚合物在基材的表面上并且形成沉积材料的轮廓。 使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。 去除聚合物间隔物。

公开(公告)号：US20080111166A1

公开(公告)日：2008-05-15

申请号：US11598242

申请日：2006-11-10

申请人： Ji Soo Kim ,  Conan Chiang ,  Daehan Choi ,  S. M. Reza Sadjadi ,  Michael Goss

发明人： Ji Soo Kim ,  Conan Chiang ,  Daehan Choi ,  S. M. Reza Sadjadi ,  Michael Goss

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

摘要翻译： 提供了一种用于形成半导体器件的方法。 栅极堆叠形成在衬底的表面上。 提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相 聚合物在基材的表面上并且形成沉积材料的轮廓。 使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。 去除聚合物间隔物。

公开(公告)号：US07311852B2

公开(公告)日：2007-12-25

申请号：US09820695

申请日：2001-03-30

申请人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

发明人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

IPC分类号： H01L21/3065

CPC分类号： H01L21/7681 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807

摘要： A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

摘要翻译： 一种半导体制造工艺，其中低k电介质层被等离子体蚀刻，对上覆掩模层具有选择性。 蚀刻剂气体可以是无氧的并且包括氟碳反应物，氮反应物和任选的载气，所述碳氟反应物和氮反应物以流速供给到等离子体蚀刻反应器的室，使得碳氟化合物反应物流速为 小于氮气反应物流量。 低k电介质层的蚀刻速率可以比二氧化硅，氮化硅，氮氧化硅或碳化硅掩模层的蚀刻速率高至少5倍。 该方法对于在形成结构如镶嵌结构中蚀刻0.25微米和较小的接触或通孔开口是有用的。

公开(公告)号：US07166535B2

公开(公告)日：2007-01-23

申请号：US10430013

申请日：2003-05-06

申请人： Si Yi Li ,  S. M. Reza Sadjadi ,  James V. Tietz

发明人： Si Yi Li ,  S. M. Reza Sadjadi ,  James V. Tietz

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/31116 ,  H01L21/32137

摘要： A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

摘要翻译： 用于等离子体蚀刻碳化硅的方法，其具有对材料的上覆和/或下层介电层的选择性。 介电材料可以包括二氧化硅，氮氧化硅，氮化硅或包括有机低k材料的各种低k电介质材料。 蚀刻气体包括诸如Cl 2的含氯气体，诸如O 2的含氧气体和诸如Ar的载气。 为了实现对这种介电材料的期望的选择性，选择等离子体蚀刻气体化学物质以在较慢的速率蚀刻电介质材料时实现所需的碳化硅蚀刻速率。 该方法可用于选择性蚀刻氢化碳化硅蚀刻停止层或碳化硅衬底。

公开(公告)号：US06962879B2

公开(公告)日：2005-11-08

申请号：US09820694

申请日：2001-03-30

申请人： Helen H. Zhu ,  David R. Pirkle ,  S. M. Reza Sadjadi ,  Andrew S. Li

发明人： Helen H. Zhu ,  David R. Pirkle ,  S. M. Reza Sadjadi ,  Andrew S. Li

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76813

摘要： A semiconductor manufacturing process wherein silicon nitride is plasma etched with selectivity to an overlying and/or underlying dielectric layer such as a silicon oxide or low-k material. The etchant gas includes a fluorocarbon reactant and an oxygen reactant, the ratio of the flow rate of the oxygen reactant to that of the fluorocarbon reactant being no greater than 1.5. The etch rate of the silicon nitride can be at least 5 times higher than that of the oxide. Using a combination of CH3F and O2 with optional carrier gasses such as Ar and/or N2, it is possible to obtain nitride:oxide etch rate selectivities of over 40:1. The process is useful for simultaneously removing silicon nitride in 0.25 micron and smaller contact or via openings and wide trenches in forming structures such as damascene and self-aligned structures.

摘要翻译： 半导体制造工艺，其中氮化硅被等离子体蚀刻，对上覆和/或下层介电层（例如氧化硅或低k材料）具有选择性。 蚀刻剂气体包括氟碳反应物和氧反应物，氧反应物的流速与氟碳反应物的流速之比不大于1.5。 氮化硅的蚀刻速率可以比氧化物的蚀刻速度高5倍以上。 使用CH 3 3 F和O 2 2的组合与可选的载气如Ar和/或N 2 N组合，可以获得氮化物 ：氧化物蚀刻速率选择性超过40：1。 该方法对于同时去除0.25微米和更小的接触或通孔开口和宽沟槽中的氮化硅在形成结构如镶嵌和自对准结构中是有用的。

公开(公告)号：US06495470B2

公开(公告)日：2002-12-17

申请号：US08580532

申请日：1995-12-29

申请人： S. M. Reza Sadjadi ,  Mansour Moinpour ,  Te Hua Lin ,  Farhad K. Moghadam

发明人： S. M. Reza Sadjadi ,  Mansour Moinpour ,  Te Hua Lin ,  Farhad K. Moghadam

IPC分类号： H01L21461

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contact opening is etched through the doped oxide layer between the conductive features such that the oxide spacers are exposed within the contact opening.

摘要翻译： 一种在半导体衬底上形成两个导电特征之间的接触开口的方法。 形成与导电特征相邻的氧化物间隔物。 然后在半导体衬底上沉积掺杂的氧化物层。 最后，通过导电特征之间的掺杂氧化物层蚀刻接触开口，使得氧化物间隔物暴露在接触开口内。

公开(公告)号：US5883436A

公开(公告)日：1999-03-16

申请号：US802285

申请日：1997-02-20

申请人： S. M. Reza Sadjadi ,  Mansour Moinpour ,  Te Hua Lin ,  Farhad K. Moghadam

发明人： S. M. Reza Sadjadi ,  Mansour Moinpour ,  Te Hua Lin ,  Farhad K. Moghadam

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/34 ,  H01L23/48

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contact opening is etched through the doped oxide layer between the conductive features such that the oxide spacers are exposed within the contact opening.

公开(公告)号：US5705419A

公开(公告)日：1998-01-06

申请号：US281525

申请日：1994-07-27

申请人： Jeffrey Robert Perry ,  S. M. Reza Sadjadi ,  Kristen Ann Luttinger

发明人： Jeffrey Robert Perry ,  S. M. Reza Sadjadi ,  Kristen Ann Luttinger

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/115 ,  Y10S438/954 ,  Y10S438/963

摘要： In the manufacture of memory cells, horizontal etching is controlled in a manner which prevents the formation of stringers between adjacent cells without undercutting the sidewalls of a memory cell.

摘要翻译： 在存储单元的制造中，以防止相邻单元之间的桁条形成而不会削弱存储单元的侧壁的方式来控制水平蚀刻。