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111 条记录 (耗时 0.032 秒)

    MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    54.
    发明申请
    MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
    存储器件及其操作方法

    公开(公告)号：US20150294724A1

    公开(公告)日：2015-10-15

    申请号：US14605433

    申请日：2015-01-26

    申请人： Sang-wan NAM ,  Kyung-min KANG

    发明人： Sang-wan NAM ,  Kyung-min KANG

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C7/14 ,  G11C16/0483

    摘要： According to example embodiments, a memory device includes a memory cell array, a controller including a normal program controller and a dummy program controller, and a driver. The memory cell array includes a first memory block on a substrate. The first memory block includes a plurality of cell strings on the substrate extending in a vertical direction. The normal program controller is configured to generate a first control signal for programming normal cells of a selected cell string that is selected based on an address received by the controller. The dummy program controller is configured to generate a second control signal for programming at least one dummy cell included in each of the plurality of cell strings before generation of the first control signal. The driver is configured to apply a first operation voltage set for programming the normal cells of the selected cell string to the first memory block in response to the first controller signal. The driver is configured to apply a second operation voltage set for programming the at least one dummy cell to the first memory block in response to the second control signal.

    摘要翻译： 根据示例实施例，存储器设备包括存储单元阵列，包括正常程序控制器和虚拟程序控制器的控制器以及驱动器。 存储单元阵列包括衬底上的第一存储块。 第一存储块包括在垂直方向上延伸的衬底上的多个单元串。 正常程序控制器被配置为产生用于根据由控制器接收的地址选择的所选择的单元串的正常单元编程的第一控制信号。 虚拟程序控制器被配置为产生第二控制信号，用于在生成第一控制信号之前对包括在多个单元串中的每一个中的至少一个虚拟单元进行编程。 驱动器被配置为响应于第一控制器信号将针对所选择的单元串的正常单元编程的第一操作电压施加到第一存储器块。 驱动器被配置为响应于第二控制信号而将至少一个虚拟单元编程的第二操作电压设置到第一存储器块。

    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    55.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20150221387A1

    公开(公告)日：2015-08-06

    申请号：US14681748

    申请日：2015-04-08

    申请人： Sang-Wan NAM

    发明人： Sang-Wan NAM

    IPC分类号： G11C16/34 ,  G11C16/26

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  H01L27/11582

    摘要： According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

    Operating method of nonvolatile memory and method of controlling nonvolatile memory
    56.
    发明授权
    Operating method of nonvolatile memory and method of controlling nonvolatile memory 有权
    非易失性存储器的操作方法和非易失性存储器的控制方法

    公开(公告)号：US09076683B2

    公开(公告)日：2015-07-07

    申请号：US13587955

    申请日：2012-08-17

    申请人： Sang-Wan Nam ,  Kang-Bin Lee ,  Junghoon Park

    发明人： Sang-Wan Nam ,  Kang-Bin Lee ,  Junghoon Park

    IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/34

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

    摘要： An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.

    摘要翻译： 一种非易失性存储器的操作方法，包括多个单元串，具有多个存储单元的每个单元串和堆叠在基板上的串选择晶体管，包括检测多个单元串中的串选择晶体管的阈值电压 ; 根据检测到的阈值电压调整提供给串选择晶体管的电压; 以及将调整后的电压施加到串选择晶体管，以在编程操作期间选择或取消选择多个单元串。

    ERASE METHOD OF NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE EMPLOYING THE SAME
    57.
    发明申请
    ERASE METHOD OF NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE EMPLOYING THE SAME 有权
    非易失性存储器件的擦除方法及其使用的存储器件

    公开(公告)号：US20150179235A1

    公开(公告)日：2015-06-25

    申请号：US14501361

    申请日：2014-09-30

    申请人： SANG-WAN NAM

    发明人： SANG-WAN NAM

    IPC分类号： G11C7/00 ,  G11C11/16 ,  G11C13/00 ,  G11C16/16

    CPC分类号： G11C16/16 ,  G11C11/16 ,  G11C16/0483 ,  G11C16/3445

    摘要： A method of erasing a nonvolatile memory device which includes a plurality of memory blocks includes receiving an erase command; erasing a selected memory block among the plurality of memory blocks in response to the erase command; and performing an operation of checking whether a threshold voltage of a selection transistor connected to at least one selection line for selecting strings included in the selected memory block is changed while performing an erase verification operation for checking whether the selected memory block is normally erased.

    摘要翻译： 擦除包括多个存储块的非易失性存储器件的方法包括接收擦除命令; 响应于所述擦除命令，擦除所述多个存储块中的所选存储块; 并且执行检查连接到选择晶体管的选择晶体管的阈值电压的操作，以便在执行用于检查所选择的存储块是否被正常擦除的擦除验证操作期间改变与包括在所选择的存储块中的选择串的选择线的选择晶体管的阈值电压。

    Nonvolatile memory device and memory system including the same
    58.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US08891307B2

    公开(公告)日：2014-11-18

    申请号：US13620002

    申请日：2012-09-14

    申请人： Sang-Wan Nam

    发明人： Sang-Wan Nam

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/04 ,  G11C16/24 ,  H01L27/1157 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a first NAND string and a second NAND string. The first NAND string include a first string selection transistor, a first ground selection transistor having a threshold voltage higher than a threshold voltage of the first string selection transistor, and first memory cells stacked on a substrate. The a second NAND string includes a second string selection transistor, a second ground selection transistor having a threshold voltage higher than a threshold voltage of the second string selection transistor, and second memory cells stacked on the substrate. A first selection line may connect the first string selection line and the first ground selection line, and a second selection line may connect the second selection line and the second ground selection line. The first and second selection lines may be electrically isolated from each other.

    摘要翻译： 根据本发明构思的示例实施例，非易失性存储器件包括第一NAND串和第二NAND串。 第一NAND串包括第一串选择晶体管，具有高于第一串选择晶体管的阈值电压的阈值电压的第一接地选择晶体管和堆叠在基板上的第一存储单元。 第二NAND串包括第二串选择晶体管，具有高于第二串选择晶体管的阈值电压的阈值电压的第二接地选择晶体管，以及堆叠在基板上的第二存储单元。 第一选择线可以连接第一串选择线和第一接地选择线，并且第二选择线可以连接第二选择线和第二接地选择线。 第一选择线和第二选择线可以彼此电隔离。

    Nonvolatile memory device with 3D memory cell array
    59.
    发明授权
    Nonvolatile memory device with 3D memory cell array 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US08570808B2

    公开(公告)日：2013-10-29

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。