公开(公告)号：US20060028573A1

公开(公告)日：2006-02-09

申请号：US11177451

申请日：2005-07-07

Applicant: Byoung-Rim Seo ,  Jae-Cheon Doh ,  Yung-Cheol Kong ,  Seok-Won Lee

Inventor： Byoung-Rim Seo ,  Jae-Cheon Doh ,  Yung-Cheol Kong ,  Seok-Won Lee

IPC: H04N5/225

CPC classification number: H04N5/2254

Abstract: The invention involves an image sensor camera module and a method of fabricating the image sensor camera module. The image sensor camera module uses a single-body type lens holder defined by a hollow cylindrical body having a shoulder protruding radially inwardly from an inner surface thereof. First and second lenses therein are spaced apart by a first spacer and a filter therein is spaced from the second lens by a second spacer. An image sensor is adhered to a lower rim of the body, and the filter is adhered to an upper rim thereof. All optical elements within the lens holder thus are affixed in fixed relative position compatible with a predefined focal length and axis. Moreover, the adhesively sealed interior of the body of the image sensor camera module prevents particulate contamination.

公开(公告)号：US20050258502A1

公开(公告)日：2005-11-24

申请号：US11130586

申请日：2005-05-16

Applicant: Yung-Cheol Kong ,  Jae-Cheon Doh ,  Byoung-Rim Seo ,  Seok-Won Lee

Inventor： Yung-Cheol Kong ,  Jae-Cheon Doh ,  Byoung-Rim Seo ,  Seok-Won Lee

IPC: H01L27/14 ,  H01L23/00 ,  H01L23/12 ,  H01L27/146 ,  H01L31/0203 ,  H01L31/10 ,  H04N5/225 ,  H04N5/335 ,  H04N5/374

CPC classification number: H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/0232 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: A chip package, an image sensor module including the same and a manufacturing method thereof. The chip package includes an image sensor chip having a plurality of bonding pads, a packaging substrate having a plurality of connection pads, an adhesive insulator, a plurality of conductive fillers, and a sealing insulator. The packaging substrate is mounted on the image sensor chip through the adhesive insulator, so that a light receiving area of the image sensor chip and an opening of the packaging substrate are vertically aligned. A plurality of through holes are formed to penetrate from portions of the connection pads to the packaging substrate. The through holes may be filled with the conductive fillers that are electrically connected between the bonding pads and the connection pads. The sealing insulator may protect the connective fillers.

Abstract translation: 芯片封装，包括该芯片封装的图像传感器模块及其制造方法。 芯片封装包括具有多个焊盘的图像传感器芯片，具有多个连接焊盘的封装基板，粘合绝缘体，多个导电填料和密封绝缘体。 通过粘合绝缘体将封装基板安装在图像传感器芯片上，使得图像传感器芯片的光接收区域和封装基板的开口垂直对齐。 多个通孔形成为从连接焊盘的部分穿透到封装基板。 通孔可以填充有电连接在接合焊盘和连接焊盘之间的导电填料。 密封绝缘子可以保护连接填料。

公开(公告)号：US06190924B1

公开(公告)日：2001-02-20

申请号：US09224654

申请日：1998-12-30

Applicant: Seok Won Lee

Inventor： Seok Won Lee

IPC: H01L2100

CPC classification number: H01L28/56

Abstract: There is provided a method for fabricating a ferroelectric capacitor which comprises the steps of: forming a bottom electrode over a substrate on which a predetermined lower structure is formed; forming a thin film of polycrystalline strontium bismuth tantalate (SBT) over the entire structure; forming an amorphous thin film of SBT on the polycrystalline film of SBT; and forming an upper electrode on the amorphous film of SBT. Though the amorphous thin film of SBT is lower in dielectric constant than the polycrystalline thin film of SBT so as not to have the properties of ferroelectric, it does not have crystalline grain boundary and, thus, does not form the path for transferring material. Therefore, the amorphous thin film of SBT can block the path of leakage current. It also results in complement of bismuth lost in the processes of deposition and thermal treatment for crystallization of the ferroelectric film of SBT at a high temperature.

Abstract translation: 提供一种用于制造铁电电容器的方法，其包括以下步骤：在其上形成有预定的下部结构的基板上形成底部电极; 在整个结构上形成多晶锶钽酸铋薄膜（SBT）; 在SBT的多晶膜上形成SBT的无定形薄膜; 并在SBT的非晶膜上形成上电极。 虽然SBT的非晶薄膜的介电常数比SBT的多晶薄膜低，但不具有铁电性质，但不具有晶界，因此不会形成转印材料的路径。 因此，SBT的非晶薄膜可以阻挡漏电流的路径。 这也导致在高温下SBT的铁电体膜的沉积和热处理过程中失去的铋的补充。

公开(公告)号：US20160293539A1

公开(公告)日：2016-10-06

申请号：US15067833

申请日：2016-03-11

Applicant: JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

Inventor： JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

IPC: H01L23/528 ,  H01L27/24 ,  H01L23/522 ,  H01L27/115

CPC classification number: H01L27/2481 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

Abstract translation: 如下提供三维半导体器件。 基板包括接触区域，虚拟区域和单元阵列区域。 堆叠结构包括垂直堆叠在基板上的电极。 电极堆叠成在接触区域上具有第一分级结构，在虚拟区域中具有第二阶梯结构。 第二阶梯结构中的至少两个相邻电极的端部具有垂直对准的第一侧壁，使得第一侧壁的水平位置基本相同。

公开(公告)号：US09449870B2

公开(公告)日：2016-09-20

申请号：US14943532

申请日：2015-11-17

Applicant: Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

Inventor： Dongseog Eun ,  Young-Ho Lee ,  Joonhee Lee ,  Seok-won Lee ,  Yoocheol Shin

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/441 ,  H01L27/24

CPC classification number: H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

公开(公告)号：US08742389B2

公开(公告)日：2014-06-03

申请号：US13655634

申请日：2012-10-19

Applicant: Seok-won Lee

Inventor： Seok-won Lee

IPC: H01L29/02

CPC classification number: H01L27/249 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226

Abstract: According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate.

Abstract translation: 根据示例性实施例，可变电阻存储器件可以包括存储单元，其中字线和可变电阻层之间的接触区域几乎是恒定的。 可变电阻存储器件可以包括在衬底上的垂直电极，顺序地交替堆叠在衬底上的水平电极层和绝缘层。 水平电极层和绝缘层可以与垂直电极相邻。 可变电阻层可以在垂直电极与水平电极层之间。 与基板相邻的水平电极层之一的厚度可以比与衬底间隔开的另一个水平电极层的厚度厚。

公开(公告)号：US08604614B2

公开(公告)日：2013-12-10

申请号：US13073250

申请日：2011-03-28

Applicant: Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

Inventor： Heung-kyu Kwon ,  Seok-won Lee ,  Hyon-chol Kim ,  Su-chang Lee ,  Chi-young Lee

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/00 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

公开(公告)号：US20130193395A1

公开(公告)日：2013-08-01

申请号：US13655634

申请日：2012-10-19

Applicant: Seok-won LEE

Inventor： Seok-won LEE

IPC: H01L27/24

CPC classification number: H01L27/249 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226

Abstract: According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate.

Abstract translation: 根据示例性实施例，可变电阻存储器件可以包括存储单元，其中字线和可变电阻层之间的接触区域几乎是恒定的。 可变电阻存储器件可以包括在衬底上的垂直电极，顺序地和交替地堆叠在衬底上的水平电极层和绝缘层。 水平电极层和绝缘层可以与垂直电极相邻。 可变电阻层可以在垂直电极与水平电极层之间。 与基板相邻的水平电极层之一的厚度可以比与衬底间隔开的另一个水平电极层的厚度厚。

公开(公告)号：US20130144437A1

公开(公告)日：2013-06-06

申请号：US13529147

申请日：2012-06-21

Applicant: Seok Won Lee ,  Woo Sung Yang

Inventor： Seok Won Lee ,  Woo Sung Yang

IPC: G05B15/00

CPC classification number: G01L5/161 ,  B25J13/085 ,  B62D57/032

Abstract: Disclosed is a module for measuring repulsive force for a walking robot. More specifically the module includes a base frame and plurality of installation units provided on the base frame and surrounded by a plurality of side surfaces configured as inclined surfaces having a predetermined angle and a top surface formed in a horizontal plane. The module also includes a 1-axis force sensor provided on each side surface and the top surface of the installation unit. A control unit calculates a sum force of the respective installation units from measurement data of the force sensor and calculates the ground reaction force (GRF) by integrating the sum force of the respective installation units.

Abstract translation: 公开了一种用于测量步行机器人的排斥力的模块。 更具体地，该模块包括基架和设置在基架上并被构造成具有预定角度的倾斜表面的多个侧表面以及在水平面中形成的顶表面包围的多个安装单元。 模块还包括设置在安装单元的每个侧表面和顶表面上的1轴力传感器。 控制单元根据力传感器的测量数据计算各个安装单元的总和力，并且通过对各个安装单元的和力进行积分来计算地面反作用力（GRF）。

公开(公告)号：US07863702B2

公开(公告)日：2011-01-04

申请号：US11150825

申请日：2005-06-10

Applicant: Byoung-Rim Seo ,  Jae-Cheon Do ,  Yung-Cheol Kong ,  Seok-Won Lee

Inventor： Byoung-Rim Seo ,  Jae-Cheon Do ,  Yung-Cheol Kong ,  Seok-Won Lee

IPC: H01L29/78

CPC classification number: H01L27/14625 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: An image sensor package assembling method includes providing a substrate on which a plurality of image sensors are mounted; providing a housing strip having a plurality of housings arranged corresponding to an arrangement of the image sensors on the substrate, each of the housings having an aperture corresponding to an active surface of the corresponding image sensor and a cavity enclosing an edge of the corresponding image sensor; attaching a transparent cover plate sealing the apertures of the housings on the housing strip after attaching the housing strip on the substrate; and separating image sensor packages from each other by successively cutting the transparent cover, the housing strip and the substrate. Increased yield and production efficiency can be realized.

Abstract translation: 图像传感器封装组装方法包括提供其上安装有多个图像传感器的基板; 提供具有多个壳体的壳体带，所述多个壳体对应于所述基板上的所述图像传感器的布置而布置，每个所述壳体具有对应于相应图像传感器的有效表面的孔，以及封闭相应图像传感器的边缘的空腔 ; 在将所述壳体条附接到所述基底上之后，附接透明盖板，其将所述壳体的所述孔密封在所述壳体条上; 并通过连续地切割透明盖，壳体条和基底来分离图像传感器封装。 可以实现提高产量和生产效率。