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    Probe card and test system for semiconductor wafers
    52.
    发明授权
    Probe card and test system for semiconductor wafers 失效
    半导体晶圆探针卡和测试系统

    公开(公告)号：US06359456B1

    公开(公告)日：2002-03-19

    申请号：US09929388

    申请日：2001-08-14

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1073

    CPC分类号： G01R1/073 ,  G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

    Test carrier with molded interconnect for testing semiconductor components
    53.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06353326B2

    公开(公告)日：2002-03-05

    申请号：US09143300

    申请日：1998-08-28

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483

    摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

    摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。

    Method for forming coaxial silicon interconnects
    54.
    发明授权
    Method for forming coaxial silicon interconnects 失效
    形成同轴硅互连的方法

    公开(公告)号：US6028436A

    公开(公告)日：2000-02-22

    申请号：US982328

    申请日：1997-12-02

    申请人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    发明人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R31/02

    CPC分类号： G01R31/2886 ,  G01R1/0408

    摘要： An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon containing insulation and a metal for shielding the trace from "cross-talk" and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.

    摘要翻译： 用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。 接触构件覆盖有绝缘层和通过导电迹线连接到测试电路的导电盖。 该痕迹覆盖有含硅绝缘体和金属的同轴层，用于屏蔽“串扰”和其他干扰的痕迹。 用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片的热膨胀特性相匹配的热膨胀特性并提供干净的信号。

    Hybrid interconnect and system for testing semiconductor dice
    55.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效
    混合互连和半导体骰子测试系统

    公开(公告)号：US6025731A

    公开(公告)日：2000-02-15

    申请号：US821468

    申请日：1997-03-21

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R1/73

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    摘要翻译： 提供用于与半导体管芯进行电连接的互连。 互连包括具有整体形成的接触构件的基板，其构造成电接触管芯上相应的接触位置。 互连还包括与衬底分开形成的导体图案，然后与接触构件电气连接到衬底。 导体可以安装到类似于TAB带的多层胶带上，或者可以直接粘合到基底上。 此外，每个导体可以包括与对应的接触构件对准的开口，并且填充有诸如导电粘合剂或焊料的导电材料。 导电材料电连接接触构件和导体，并且提供膨胀接头以允许导体的膨胀而不会压紧接触构件。 还提供了一种用于测试包括互连的骰子的系统，以及用于测试晶片的系统，其中互连形成为探针卡。

    Method for testing semiconductor components
    57.
    发明授权
    Method for testing semiconductor components 失效
    半导体元件测试方法

    公开(公告)号：US06396291B1

    公开(公告)日：2002-05-28

    申请号：US09723101

    申请日：2000-11-28

    申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

    IPC分类号： G01R3102

    CPC分类号： G01R1/0466 ,  G01R1/0483

    摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

    摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

    Method of forming coaxial silicon interconnects
    58.
    发明授权
    Method of forming coaxial silicon interconnects 失效
    用于测试半导体器件的同轴硅互连

    公开(公告)号：US06392430B1

    公开(公告)日：2002-05-21

    申请号：US09722866

    申请日：2000-11-27

    申请人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    发明人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    IPC分类号： G01R3102

    CPC分类号： G01R31/2886 ,  G01R1/0408

    摘要： An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon-containing insulation and a metal for shielding the trace from “crosstalk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.

    摘要翻译： 用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。 接触构件覆盖有绝缘层和通过导电迹线连接到测试电路的导电盖。 该迹线覆盖有含硅绝缘体和金属的同轴层，用于屏蔽“串扰”和其他干扰的迹线。 用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片的热膨胀特性相匹配的热膨胀特性并提供干净的信号。

    Probe card and testing method for semiconductor wafers
    59.
    发明授权
    Probe card and testing method for semiconductor wafers 有权
    半导体晶圆的探针卡和测试方法

    公开(公告)号：US06275052B1

    公开(公告)日：2001-08-14

    申请号：US09303367

    申请日：1999-04-30

    申请人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    发明人： David R. Hembree ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  C. Patrick Doherty ,  Andrew J. Krivy

    IPC分类号： G01R1073

    CPC分类号： G01R1/073 ,  G01R31/2886

    摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.

    摘要翻译： 提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。 探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。 探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。 探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。 互连衬底可以由具有穿透突起的凸起接触构件的硅形成。 或者，接触构件可以形成为用于测试凸起的晶片的凹陷。 膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。 探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。