利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

149 条记录 (耗时 0.032 秒)

    Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
    56.
    发明授权
    Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 失效
    使用金属锗合金降低金属硅化物的接触电阻的方法和结构

    公开(公告)号：US06331486B1

    公开(公告)日：2001-12-18

    申请号：US09519897

    申请日：2000-03-06

    申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

    发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

    IPC分类号： H01L244

    CPC分类号： H01L21/28518

    摘要： A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.

    摘要翻译： 提供了一种降低金属硅化物与含硅衬底的接触电阻的方法。 该方法包括首先在含硅衬底上形成金属锗层。 可以在金属锗层上形成任选的氧阻挡层。 接下来，含有金属锗层的结构在有效地将金属锗层的至少一部分转化为基本上不可蚀刻的金属硅化物层的同时，在衬底和硅化物层之间形成Si-Ge中间层的温度下进行退火 。 在退火之后，从衬底去除可选的氧阻挡层和任何剩余的金属锗层。

    Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging
    57.
    发明授权
    Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging 有权
    使用金属硅合金自发对准形成硅化物接触的方法，用于有限的硅消耗和减少桥接

    公开(公告)号：US06323130B1

    公开(公告)日：2001-11-27

    申请号：US09515033

    申请日：2000-03-06

    申请人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

    发明人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).

    摘要翻译： 一种在金属硅化物接触形成期间显着降低Si消耗和桥接的方法，包括以下步骤：（a）在含有电接触的电子器件的含硅衬底上形成金属硅合金层，所述合金层中的所述硅为 小于约30原子％，所述金属为Co，Ni或其混合物; （b）在约300℃至约500℃的温度下退火所述金属硅合金层，以便与所述金属硅合金或纯金属相比形成基本不可蚀刻的富金属硅化物层; （c）在非硅区域上有选择地去除任何未反应的金属硅合金; 和（d）在有效形成处于其最低电阻相的金属硅化物相的条件下退火所述富金属硅化物层。 可以在退火步骤（b）之前在金属硅合金层上形成任选的氧阻挡层。

    Method for forming electromigration-resistant structures by doping
    58.
    发明授权
    Method for forming electromigration-resistant structures by doping 有权
    通过掺杂形成电迁移结构的方法

    公开(公告)号：US06268291B1

    公开(公告)日：2001-07-31

    申请号：US09204185

    申请日：1998-12-03

    申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Christopher Carr Parks ,  Kenneth Parker Rodbell ,  Roger Yen-Luen Tsai

    发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Christopher Carr Parks ,  Kenneth Parker Rodbell ,  Roger Yen-Luen Tsai

    IPC分类号： H01L2100

    CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/29099 ,  H01L2924/00

    摘要： A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle. In the second method, a copper seed layer is first deposited into a receptacle, a copper composition containing impurities is then electrodeposited into the receptacle and the electronic structure is annealed so that impurities diffuse into the copper seed layer. In the third method, a barrier layer is first deposited into a receptacle, dopant ions are then implanted into the barrier layer with a copper seed layer subsequently deposited on top of the barrier layer. An annealing process for the electronic structure is then carried out such that dopant ions diffuse into the copper seed layer. The present invention method may further include the step of ion-implanting at least one element into a surface layer of the copper conductor after the conductor is first planarized. The surface layer may have a thickness between about 30 Å and about 500 Å. At least one element may be selected from Co, Al, Sn, In, Ti and Cr.

    摘要翻译： 本发明公开了一种在电子结构中形成铜导体的方法，该方法是先将铜组合物沉积在形成于电子结构中的容器中，然后向铜组合物中添加杂质使其电迁移阻力得到改善。 在该方法中，铜组合物可以通过各种技术沉积，例如电镀，物理气相沉积和化学气相沉积。 可植入的杂质包括C，O，Cl，S和N的杂质，其浓度范围为约0.01ppm至约1000ppm。 可以通过三种不同的方法加入杂质。 在第一种方法中，首先将铜种子层沉积到容器中，并在种子层上进行离子注入工艺，然后将铜电镀到容器中。 在第二种方法中，首先将铜种子层沉积到容器中，然后将含有杂质的铜组合物电沉积到容器中，并且将电子结构退火，使得杂质扩散到铜籽晶层中。 在第三种方法中，首先将阻挡层沉积到容器中，然后将掺杂剂离子注入到阻挡层中，随后将铜籽晶层沉积在阻挡层的顶部上。 然后进行电子结构的退火处理，使得掺杂剂离子扩散到铜籽晶层中。 本发明的方法还可以包括在导体首先平坦化之后将至少一种元素离子注入到铜导体的表面层中的步骤。 表面层可以具有在约和之间的厚度。 至少一种元素可以选自Co，Al，Sn，In，Ti和Cr。

    Low temperature selective growth of silicon or silicon alloys
    60.
    发明授权
    Low temperature selective growth of silicon or silicon alloys 失效
    硅或硅合金的低温选择性生长

    公开(公告)号：US5634973A

    公开(公告)日：1997-06-03

    申请号：US587029

    申请日：1996-01-16

    申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  C30B33/06

    CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

    摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

    摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。