公开(公告)号：US06941815B2

公开(公告)日：2005-09-13

申请号：US10173732

申请日：2002-06-19

申请人： Yasuo Onose ,  Junichi Horie ,  Seiji Kuryu ,  Akihiko Saito ,  Norio Ichikawa ,  Atsuo Watanabe ,  Satoshi Shimada

发明人： Yasuo Onose ,  Junichi Horie ,  Seiji Kuryu ,  Akihiko Saito ,  Norio Ichikawa ,  Atsuo Watanabe ,  Satoshi Shimada

IPC分类号： G01L9/00 ,  H01L29/84 ,  G01L9/04

CPC分类号： G01L9/0073 ,  G01L9/0042

摘要： A sensor with built-in circuits can be improved in the stability of the operation or characteristics. A circuit region and a sensor region are covered by a passivation film. The sensor region is partially covered by the passivation film. The sensor region and circuit region are protected by the passivation film, and an effect of the passivation film on the mechanical displacement of a diaphragm portion can be alleviated so that the sensor with built-in circuits may be improved in the stability of the operation or characteristics.

摘要翻译： 具有内置电路的传感器可以提高操作的稳定性或特性。 电路区域和传感器区域被钝化膜覆盖。 传感器区域被钝化膜部分覆盖。 传感器区域和电路区域被钝化膜保护，并且可以减轻钝化膜对隔膜部分的机械位移的影响，使得具有内置电路的传感器可以在操作的稳定性方面得到改善，或者 特点

公开(公告)号：US06921461B2

公开(公告)日：2005-07-26

申请号：US10450133

申请日：2001-11-22

申请人： Atsuo Watanabe ,  Takahisa Hikida ,  Atsushi Watanabe

发明人： Atsuo Watanabe ,  Takahisa Hikida ,  Atsushi Watanabe

IPC分类号： D21F3/00 ,  D21F3/02 ,  D21G9/00

CPC分类号： D21F3/0227 ,  D21F3/0236 ,  Y10S162/901 ,  Y10T428/24488 ,  Y10T428/24521 ,  Y10T428/24537 ,  Y10T428/2457 ,  Y10T442/2025 ,  Y10T442/2049 ,  Y10T442/2369 ,  Y10T442/2377

摘要： A papermaking belt of improved durability capable of preventing a crack from progressing into the which includes a reinforcing substrate embedded in an elastic material, and the elastic material containing a surface layer, a back layer and an intermediate layer located between the surface layer and the back layer and having a thick part containing a thickness in the belt thickness direction along the belt traveling direction in the said intermediate layer. The thick part can also be exposed on the belt surface through the surface layer, the thick part is preferably made of a low-hardness elastic material and the surface layer is preferably made of a high-hardness elastic material.

摘要翻译： 一种具有改进的耐久性的造纸带，其能够防止其进入包括嵌入在弹性材料中的增强基板，并且弹性材料包含位于表面层和背面之间的表面层，背层和中间层 并且在所述中间层中具有沿带传送方向的带厚度方向上的厚度的厚部。 厚部也可以通过表面层暴露在带表面上，厚部优选由低硬度弹性材料制成，表面层优选由高硬度弹性材料制成。

公开(公告)号：US06885067B2

公开(公告)日：2005-04-26

申请号：US10791764

申请日：2004-03-04

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/77 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H04M3/00 ,  H04M3/18 ,  H01L27/01

CPC分类号： H01L29/66681 ,  G09G3/28 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66265 ,  H01L29/66674 ,  H01L29/7317 ,  H01L29/7824 ,  H04M3/005 ,  H04M3/18 ,  H04M2201/06

摘要： A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.

摘要翻译： 一种用于汽车发动机控制单元的电力IC，其结合有至少一个半导体器件，该半导体器件包括形成在SOI衬底上的N沟道绝缘栅场效应晶体管，具有浓度高于N- 型层与与晶体管的栅极氧化膜接触的p体层接触。 在掩埋氧化膜的界面上，覆盖硅基板​​中的晶体管的p体层和漏电极的源极 - 漏极距离的至多95％的区域形成高浓度N型层， 硅衬底与场氧化物膜和接触漏电极的高浓度N型层接触。

公开(公告)号：US06750513B2

公开(公告)日：2004-06-15

申请号：US10393951

申请日：2003-03-24

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L2701

CPC分类号： H01L29/66681 ,  G09G3/28 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66265 ,  H01L29/66674 ,  H01L29/7317 ,  H01L29/7824 ,  H04M3/005 ,  H04M3/18 ,  H04M2201/06

摘要： An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.

摘要翻译： 在SOI衬底上的N沟道MOS场效应晶体管，其包括经由场氧化膜设置的源电极，漏极和栅电极，栅极氧化膜，高浓度P型层，高浓度N型层 与源电极和栅极氧化膜接触，接触漏电极的高浓度N型层，与高浓度P型和N型层接触的p体层和栅氧化膜。 在该晶体管中，具有高于与p体层接触的漏极区域的浓度的N型层构成覆盖源极 - 漏极距离的至多95％的区域。 此外，在漏电极下方的掩埋氧化膜附近提供浓度为3×10 16 / cm 3至1×10 22 / cm 3的N型区域。

公开(公告)号：US5836860A

公开(公告)日：1998-11-17

申请号：US571232

申请日：1995-12-12

申请人： Atsuo Watanabe ,  Kenjiro Nakayama ,  Tatsuyuki Abe

发明人： Atsuo Watanabe ,  Kenjiro Nakayama ,  Tatsuyuki Abe

IPC分类号： F16C13/00 ,  G11B5/84 ,  B21B31/08

CPC分类号： F16C13/00 ,  G11B5/84 ,  Y10T29/49563 ,  Y10T29/53104 ,  Y10T428/257 ,  Y10T428/2933

摘要： In a resin roll 5 for calendering a magnetic recording medium, a surface portion 3a of a thermosetting resin outer layer 3 has high storage elastic modulus (E') of 5.times.10.sup.10 to 5.times.10.sup.11 dyn/cm.sup.2 at a temperature of 50.degree. to 150.degree. C. at a frequency of 10 hertz (Hz). At the surface portion of the thermosetting resin outer layer, the expression representing the relation between storage elastic modulus (E') and the Poisson's ratio (.nu.) is within the following range, under the same conditions: 2.times.10.sup.-12 cm.sup.2 /dyn

摘要翻译： 在用于压延磁记录介质的树脂辊5中，热固性树脂外层3的表面部分3a在50至150℃的温度下具有5×10 10至5×10 11 dyn / cm 2的高储存弹性模量（E'）。 频率为10赫兹（Hz）。 在热固性树脂外层的表面部分，表示储存弹性模量（E'）与泊松比（nu）之间的关系的表达式在以下相同的条件下，在相同的条件下：2×10-12cm 2 / dyn（ 1-nu 2）/ E'<2×10-11 cm 2 / dyn

公开(公告)号：US5753165A

公开(公告)日：1998-05-19

申请号：US501025

申请日：1995-08-11

申请人： Atsuo Watanabe ,  Kenjiro Nakayama ,  Shunsuke Kato

发明人： Atsuo Watanabe ,  Kenjiro Nakayama ,  Shunsuke Kato

IPC分类号： B29C39/02 ,  B29C39/10 ,  B29C39/40 ,  D21G1/02 ,  A21C13/00 ,  B29C39/38

CPC分类号： B29C39/40 ,  B29C39/028 ,  B29C39/10 ,  D21G1/0246 ,  B29C2791/001 ,  B29C70/72 ,  B29L2031/324 ,  B29L2031/748 ,  Y10T29/49551 ,  Y10T29/49552 ,  Y10T29/4956 ,  Y10T29/49563

摘要： A process for producing a hard roll for use as an elastic roll for making paper calendering by casting a liquid thermosetting resin material into a space between a metal roll core and an outer mold, and thereafter heating the resin material from outside to cure a major portion of the material and to form an outer layer resin intermediate body, while cooling the resin material from the roll core side to leave a viscount liquid resin material layer inside the intermediate body. The intermediate body is subsequently cooled from outside the outer mold to contract the body, allowing an excess of the liquid material to be forced out upwardly with the contraction of the body. The material is thereafter heated from the roll core side to cure the remaining viscous liquid resin material. The hard roll can be produced without cracking due to the reaction contraction and thermal shrinkage of the thermosetting resin. The roll is usable without cracking in its surface hardness despite the influence of heat. The process is reduced in the number of steps and improved in production efficiency to ensure a low production cost.

摘要翻译： PCT No.PCT / JP94 / 02143 Sec。 371日期：1995年8月11日 102（e）日期1995年8月11日PCT 1994年12月20日PCT PCT。 公开号WO95 / 17298 日期：1995年6月29日制造用于通过将液态热固性树脂材料浇铸到金属辊芯和外模之间的空间中制造纸压延的弹性辊的硬辊的制造方法，然后从外部加热树脂材料 固化材料的主要部分并形成外层树脂中间体，同时从辊芯侧冷却树脂材料，以在中间体内留下粘液液体树脂材料层。 随后，中间体从外模外部冷却，从而使本体收缩，从而允许液体物质的过量随着身体的收缩而被向上压出。 然后将材料从辊芯侧加热以固化剩余的粘性液体树脂材料。 可以由于热固性树脂的反应收缩和热收缩而产生不产生裂纹的硬辊。 尽管受到热的影响，但辊的表面硬度也不会破裂。 该过程减少了步数，提高了生产效率，确保了低生产成本。

公开(公告)号：US5512497A

公开(公告)日：1996-04-30

申请号：US272312

申请日：1994-07-08

申请人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

发明人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265 ,  H01L21/8238

CPC分类号： H01L21/28026 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

摘要翻译： 公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

公开(公告)号：US5508549A

公开(公告)日：1996-04-16

申请号：US735948

申请日：1991-07-25

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US5506156A

公开(公告)日：1996-04-09

申请号：US279087

申请日：1994-07-22

申请人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

发明人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/8249 ,  Y10S148/009

摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

摘要翻译： 半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。 具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。 第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质 在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰 值。 在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

公开(公告)号：US5362998A

公开(公告)日：1994-11-08

申请号：US193643

申请日：1994-02-07

申请人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

发明人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/56 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A composite circuit device of bipolar transistors and MOS transistors has a series connection of an NPN transistor for pull-up and a PNP transistor for pull-down. The composite circuit device has independent base drive circuits so provided that the base of the NPN transistor for pull-up is electrically isolated from the base of the PNP transistor for pull-down during the on-off switching operation. The composite circuit device is also provided with base precharge circuitry for pre-charging the base of the PNP transistor during the off operation state thereof. A composite circuit is also provided with circuitry for enhancing the turn-on switching speed of the pull-down PNP transistor. Additionally, a composite circuit of bipolar transistors and MOS transistors is constituted by a switch having a high input impedance and low on-resistance which can be applied as a component of an electronic circuit.

摘要翻译： 双极晶体管和MOS晶体管的复合电路器件具有用于上拉的NPN晶体管和用于下拉的PNP晶体管的串联连接。 复合电路器件具有独立的基极驱动电路，使得用于上拉的NPN晶体管的基极与PNP晶体管的基极电隔离，用于在截止开关操作期间进行下拉。 复合电路器件还设置有用于在其关断操作状态期间对PNP晶体管的基极进行预充电的基极预充电电路。 复合电路还提供有用于增强下拉PNP晶体管的导通开关速度的电路。 此外，双极晶体管和MOS晶体管的复合电路由具有高输入阻抗和低导通电阻的开关构成，其可以用作电子电路的组件。