公开(公告)号：US20170148850A1

公开(公告)日：2017-05-25

申请号：US15428509

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.

公开(公告)号：US20160118483A1

公开(公告)日：2016-04-28

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US09177803B2

公开(公告)日：2015-11-03

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。

公开(公告)号：US09129843B1

公开(公告)日：2015-09-08

申请号：US14302880

申请日：2014-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka ,  Jan Hoentschel

IPC: H01F17/00 ,  H01L49/02 ,  H01L21/263 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  B23K26/00 ,  B23K26/38

CPC classification number: H01L28/10 ,  B23K26/38 ,  B23K26/53 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/66083 ,  H01L29/665 ,  H01L29/78 ,  H01L29/86

Abstract: A method of forming an inductor in a crystal semiconductor layer is provided, including generating an ion beam, directing the ion beam to a surface of the crystal semiconductor layer, applying a magnetic field to the ion beam to generate a helical motion of the ions and forming a three-dimensional helical structure in the crystal semiconductor layer by means of the ions of the ion beam.

Abstract translation: 提供一种在晶体半导体层中形成电感器的方法，包括产生离子束，将离子束引导到晶体半导体层的表面，向离子束施加磁场以产生离子的螺旋运动，以及 通过离子束的离子在晶体半导体层中形成三维螺旋结构。

公开(公告)号：US20140264347A1

公开(公告)日：2014-09-18

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US08735241B1

公开(公告)日：2014-05-27

申请号：US13747972

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Roman Boschke

IPC: H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

Abstract: Methods for forming CMOS integrated circuit structures are provided, the methods comprising performing a first implantation process for performing at least one of a halo implantation and a source and drain extension implantation into a region of a semiconductor substrate and then forming a stressor region in another region of the semiconductor substrate. Furthermore, a semiconductor device structure is provided, the structure comprising a stressor region embedded into a semiconductor substrate adjacent to a gate structure, the embedded stressor region having a surface differing along a normal direction of the surface from an interface by less than about 8 nm, wherein the interface is formed between the gate structure and the substrate.

Abstract translation: 提供了用于形成CMOS集成电路结构的方法，所述方法包括执行第一注入工艺，用于将光晕注入和源极和漏极延伸注入中的至少一个进行到半导体衬底的区域中，然后在另一区域中形成应力区域 的半导体衬底。 此外，提供了一种半导体器件结构，该结构包括嵌入到与栅极结构相邻的半导体衬底中的应力区域，所述嵌入的应力区域具有沿着表面的法线方向从界面相差小于约8nm的表面 其中所述界面形成在所述栅极结构和所述衬底之间。

公开(公告)号：US10319732B2

公开(公告)日：2019-06-11

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US20180322912A1

公开(公告)日：2018-11-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C11/225 ,  G11C16/0466 ,  G11C16/06 ,  H01L29/78391 ,  H01L29/7841

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US09871050B1

公开(公告)日：2018-01-16

申请号：US15232906

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC: H01L29/788 ,  H01L27/11531 ,  H01L27/12 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11521

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1207 ,  H01L29/42328 ,  H01L29/42336

Abstract: A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.

公开(公告)号：US20170117322A1

公开(公告)日：2017-04-27

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.