公开(公告)号：US20080237694A1

公开(公告)日：2008-10-02

申请号：US11728960

申请日：2007-03-27

申请人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

发明人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/513

摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.

摘要翻译： 本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。 在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一 高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

公开(公告)号：US20080225587A1

公开(公告)日：2008-09-18

申请号：US11686211

申请日：2007-03-14

申请人： Nicolas Nagel ,  Josef Willer

发明人： Nicolas Nagel ,  Josef Willer

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578

摘要： The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

摘要翻译： 本发明一般涉及集成电路，集成电路的制造方法以及集成存储器阵列。

公开(公告)号：US20070215986A1

公开(公告)日：2007-09-20

申请号：US11376645

申请日：2006-03-15

申请人： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert

发明人： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert

IPC分类号： H01L23/58 ,  H01L21/467

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L27/105 ,  H01L27/112

摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

摘要翻译： 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

公开(公告)号：US20070077748A1

公开(公告)日：2007-04-05

申请号：US11241877

申请日：2005-09-30

申请人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

发明人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L27/115 ,  H01L21/76838 ,  H01L27/11521 ,  H01L27/11568

摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).

摘要翻译： 半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。 沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。 每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。 因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。 根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。 因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

公开(公告)号：US07042037B1

公开(公告)日：2006-05-09

申请号：US10986060

申请日：2004-11-12

申请人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

发明人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

IPC分类号： H01L31/062

CPC分类号： H01L28/55 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有 铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜， 以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

公开(公告)号：US07009230B2

公开(公告)日：2006-03-07

申请号：US10604323

申请日：2003-07-10

申请人： Bum Ki Moon ,  Gerhard Beitel ,  Nicolas Nagel ,  Andreas Hilliger ,  Koji Yamakawa ,  Keitaro Imai

发明人： Bum Ki Moon ,  Gerhard Beitel ,  Nicolas Nagel ,  Andreas Hilliger ,  Koji Yamakawa ,  Keitaro Imai

IPC分类号： H01L29/76

CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

摘要： An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer. The second barrier layer comprises a conductive oxide.

摘要翻译： 公开了用于抑制原子或分子扩散的改进的阻挡层，例如O 2。 势垒堆叠在电容器超过插塞结构中特别有用，以防止插塞氧化，这可能不利地影响结构的可靠性。 阻挡层包括第一和第二阻挡层。 在一个实施例中，第一阻挡层包括具有失配的晶界的第一和第二子阻挡层。 亚阻挡层选自例如Ir，Ru，Pd，Rh或其合金。 通过提供错配的晶界，子阻挡层的界面阻挡氧的扩散路径。 为了进一步增强阻挡性能，使用例如快速热氧化，第一阻挡层用O 2 2钝化。 RTO在第一阻挡层的表面上形成薄的氧化物层。 氧化物层可以有利地促进第一和第二子阻挡层的晶界的失配。 第二阻挡层包括导电氧化物。

公开(公告)号：US6011284A

公开(公告)日：2000-01-04

申请号：US995845

申请日：1997-12-22

申请人： Kenji Katori ,  Nicolas Nagel ,  Koji Watanabe ,  Masahiro Tanaka

发明人： Kenji Katori ,  Nicolas Nagel ,  Koji Watanabe ,  Masahiro Tanaka

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/7687 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/55

摘要： An electronic material is expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.I is at least one sort of noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M.sub.II is at least one sort of transition metal selected from the group consisting of Hf, Ta, Zr, Nb, V, Mo and W) having a composition within the range of 90.gtoreq.a.gtoreq.40, 15.gtoreq.b.gtoreq.2, 4.ltoreq.c and a+b+c=100. A dielectric capacitor comprises: a diffusion preventing layer made of the material expressed by the composition formula M.sub.ia M.sub.IIb O.sub.c ; a lower electrode on the diffusion preventing layer; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. Another dielectric capacitor comprises: a diffusion preventing layer made of a material expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.II is at least one sort of noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M.sub.II is at least one sort of rare earth element) having a composition within the range of 90.gtoreq.a.gtoreq.40, 15.gtoreq.b.gtoreq.2, 4.ltoreq.c and a+b+c=100; a lower electrode on the diffusion preventing layer; a dielectric film on the lower electrode; and an upper electrode on the dielectric film.

摘要翻译： 电子材料由组成式MIaMIIbOc表示（其中a，b和c是原子％的组成，MI是选自Pt，Ir，Ru，Rh和Pd中的至少一种贵金属，MII 是选自组成在90以上的组成的Hf，Ta，Zr，Nb，V，Mo和W中的至少一种过渡金属）= = > = = 4，4

公开(公告)号：US5864153A

公开(公告)日：1999-01-26

申请号：US958444

申请日：1997-10-27

申请人： Nicolas Nagel ,  Kenji Katori

发明人： Nicolas Nagel ,  Kenji Katori

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/92 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A capacitor structure of a semiconductor memory cell such as a FERAM has an upper electrode less susceptible a damage even by heat-treatment in a hydrogen gas atmosphere. The capacitor structure includes a lower electrode, a capacitor thin film formed of a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the capacitor thin film. The upper electrode is made of Ru.sub.1-x O.sub.x (0.1

摘要翻译： 诸如FERAM的半导体存储单元的电容器结构具有即使在氢气气氛中进行热处理也不易受到损伤的上电极。 电容器结构包括下电极，由形成在下电极上的铁电薄膜形成的电容器薄膜和形成在电容器薄膜上的上电极。 上电极由Ru1-xOx（0.1

公开(公告)号：US08009477B2

公开(公告)日：2011-08-30

申请号：US12182714

申请日：2008-07-30

申请人： Christoph Kleint ,  Nicolas Nagel ,  Dominik Olligs ,  Matthias Markert

发明人： Christoph Kleint ,  Nicolas Nagel ,  Dominik Olligs ,  Matthias Markert

IPC分类号： G11C11/40 ,  H01L27/088 ,  H01L29/78 ,  H01L21/4763

CPC分类号： G11C5/063 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813

摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.

摘要翻译： 集成电路和形成集成电路的方法。 一个实施例包括形成在载体的表面上方的导线。 在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

公开(公告)号：US07935608B2

公开(公告)日：2011-05-03

申请号：US12131794

申请日：2008-06-02

申请人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

发明人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

摘要翻译： 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。