公开(公告)号：US5597748A

公开(公告)日：1997-01-28

申请号：US247589

申请日：1994-05-23

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5384742A

公开(公告)日：1995-01-24

申请号：US30343

申请日：1993-03-25

申请人： Tadashi Miyakawa ,  Masamichi Asano

发明人： Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/16 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418

摘要： A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.

摘要翻译： PCT No.PCT / JP91 / 01272 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT 1991年9月25日PCT公布。 出版物WO92 / 05560 日期：1992年4月2日。存储单元阵列被分成多个块。 在更改块（选择块）的数据时，将调节电压施加到另一个块（未选择块）中的存储单元的源极或控制栅极，以缓和浮动栅极和源极/漏极之间的应力，从而防止写入 错误和擦除错误。 在编程操作中，未选择的块中的存储单元的源极和漏极被均衡以控制控制栅极和源极/漏极之间的电场，并且不流过沟道电流，从而防止写入错误。 在执行负电压擦除方法时，在将未选块中的单元的源极线和字线设置为擦除电压之前，源极和字线被均衡。 在擦除操作之后释放均衡操作，从而防止未选择的单元的故障。

公开(公告)号：US5210048A

公开(公告)日：1993-05-11

申请号：US924521

申请日：1992-08-04

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US4692834A

公开(公告)日：1987-09-08

申请号：US761707

申请日：1985-08-02

申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

IPC分类号： H01L27/06 ,  H02H9/04 ,  H02H3/20

CPC分类号： H02H9/046

摘要： An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.

摘要翻译： 静电放电保护电路具有用于限制具有给定高或低电压的输入信号的电位的可变阈值，并且适用于包含响应于输入信号的输入MOS晶体管的EPROM。 保护电路与用于接收输入信号的输入端相关联。 输入端耦合到输入MOS晶体管的栅极。 保护电路还包括用于限制或抑制在可变阈值处的输入信号电位的电路元件。 输入MOS晶体管的栅极接收来自电路元件的电位限制信号。 电路元件响应给定的阈值控制电位。 当将高电压输入信号施加到输入端时，通过给定的阈值控制电位增强可变阈值。

公开(公告)号：US4556961A

公开(公告)日：1985-12-03

申请号：US379852

申请日：1982-05-19

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： G11C5/06 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C5/063 ,  G11C8/14

摘要： A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

摘要翻译： 半导体器件包括多个数据提供电路，用于产生从数据提供电路传送的多个数据的输出电路和用于将各个数据从每个数据提供电路传送到具有不同延迟时间的不同输出电路的延迟电路。 每个数据提供电路包括多行行，行解码器，用于响应于地址信号选择行行;多个存储单元阵列，包括由行行有选择地驱动并存储数据的存储单元;多个列线 以接收从存储单元阵列读出的数据，以及列解码器，用于选择所述列线。 延迟电路防止多个数据被同时输出。

公开(公告)号：US4542485A

公开(公告)日：1985-09-17

申请号：US337969

申请日：1982-01-08

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： G05F3/24 ,  G11C5/00 ,  G11C5/14 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10 ,  G11C17/08 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C5/147 ,  G05F3/242 ,  G11C17/08 ,  G11C5/00 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10

摘要： A semiconductor integrated circuit comprises a first MOS transistor connected at the drain to a power source terminal of a high potential power source and supplied at the gate with a predetermined voltage, a logic circuit including MOS transistors provided between the power source terminal and a circuit point at a potential and operating in a potential range between the high potential and the circuit point, and a circuit for making the potential at the circuit point coincide with the potential at the source of the first MOS transistor.

摘要翻译： 半导体集成电路包括：第一MOS晶体管，其在漏极处连接到高电位电源的电源端子，并在栅极处提供预定电压;逻辑电路，包括设置在电源端子与电路点之间的MOS晶体管 处于电位并且在高电位和电路点之间的电位范围内工作，并且用于使电路上的电位与第一MOS晶体管的源极处的电位一致的电路。

公开(公告)号：US4473762A

公开(公告)日：1984-09-25

申请号：US312074

申请日：1981-10-16

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： H01L27/092 ,  E05F15/632 ,  E05F15/70 ,  G05D23/20 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/78 ,  H03K5/00 ,  H03K5/13 ,  H03K17/14 ,  H03K17/687 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  G05D23/1906 ,  G05D23/20 ,  H01L27/0211 ,  H03K19/00315 ,  H03K19/00384 ,  H03K19/017 ,  H03K19/09443 ,  H03K19/09445 ,  H03K5/133 ,  H03K2005/00143 ,  H03K2005/00195

摘要： A current-controlling MOS transistor is connected between a power source and an MOS circuit. A control voltage which has a level related to temperature is applied to the gate electrode of the control MOS transistor in order to compensate for current reduction at high temperatures due to the lowering of the mobility of minority carriers. The response time of the MOS circuit is made less dependent on temperature as a result of the current compensation.

摘要翻译： 电流控制MOS晶体管连接在电源和MOS电路之间。 具有与温度相关的电平的控制电压被施加到控制MOS晶体管的栅电极，以便补偿由于少数载流子的迁移率的降低导致的高温下的电流降低。 由于电流补偿，MOS电路的响应时间较少取决于温度。

公开(公告)号：US4395724A

公开(公告)日：1983-07-26

申请号：US180435

申请日：1980-08-22

申请人： Hiroshi Iwahashi ,  Masamichi Asano

发明人： Hiroshi Iwahashi ,  Masamichi Asano

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7881

摘要： In a nonvolatile semiconductor memory device using as memory cells insulated-gate type field effect transistors each having source and drain regions, a floating gate electrode, and a control gate electrode, the width of the floating and control gate electrodes is narrower at those portions which are located over a channel between the source and drain regions in each memory cell than at those portions which are not located over the channel.

摘要翻译： 在使用各自具有源极和漏极区域的存储单元绝缘栅型场效应晶体管的非易失性半导体存储器件中，浮置栅极电极和控制栅电极，浮动栅极电极和控制栅电极的宽度在 位于每个存储器单元中的源极和漏极区域之间的通道上，而不是位于通道上方的那些部分。

公开(公告)号：US4340943A

公开(公告)日：1982-07-20

申请号：US153951

申请日：1980-05-28

申请人： Masamichi Asano ,  Hiroshi Iwahashi

发明人： Masamichi Asano ,  Hiroshi Iwahashi

IPC分类号： G11C7/12 ,  G11C11/34 ,  G11C11/408 ,  G11C11/417 ,  G11C16/04 ,  G11C16/24 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C16/0416 ,  G11C11/4085 ,  G11C11/417 ,  G11C16/24 ,  G11C7/12

摘要： A memory device utilizing metal oxide semiconductor field effect transistors (MOS FETs) formed in a semiconductor substrate. The memory device is so improved as to be accessed without a delay and as not to behave erroneously, in spite of a potential variation of data line or the semiconductor substrate. It comprises a plurality of row lines for supplying input signals, a plurality of column lines for supplying output signals, decoders for selecting any one of these lines, a plurality of memory cells connected to the row and column lines in a specific manner, a voltage sensing circuit connected to the column lines, a first potential source connected to the column lines, a second potential source for supplying the memory cells with a source voltage, and means for holding the column lines at a potential substantially equal to the voltage supplied from the second potential source when the potential of the column lines or the substrate varies.

摘要翻译： 一种利用形成在半导体衬底中的金属氧化物半导体场效应晶体管（MOS FET）的存储器件。 尽管存在数据线或半导体衬底的潜在变化，存储器件如此改进以便无延迟地被访问并且不会出错。 它包括用于提供输入信号的多条行线，用于提供输出信号的多条列线，用于选择这些线中的任何一条的解码器，以特定方式连接到行和列线的多个存储单元，电压 连接到列线的感测电路，连接到列线的第一电位源，用于向存储器单元提供源极电压的第二电位源，以及用于将列线保持在基本上等于从 当列线或衬底的电位变化时，第二电位源。

公开(公告)号：US20100030943A1

公开(公告)日：2010-02-04

申请号：US10589375

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G11C7/1027 ,  G11C7/1072

摘要： A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal.

摘要翻译： 具有与时钟信号同步的突发模式读取功能的半导体存储器包括由多个存储器单元组成的存储器阵列，用于将接收到的地址的上部组释放为存储器访问地址的同步读取控制电路和下部组 的接收地址作为与时钟信号同步的突发地址;读出放大器，用于释放由存储器地址选择的每个存储器单元的输出数据，解码器，用于解码突发地址;地址锁存器，用于锁存解码的 突发地址与时钟信号同步，用于保存输出数据并选择由地址锁存器的突发地址确定的输出数据中的相应一个的页选择器，以及用于与时钟信号同步地锁存输出数据的输出锁存器 。