公开(公告)号：US09391141B2

公开(公告)日：2016-07-12

申请号：US14628608

申请日：2015-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L21/308 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract translation: 在半导体衬底的区域中使用定向自组装（DSA）光刻图案来制造鳍结构的方法包括提供在其一侧上覆盖有浅沟槽隔离（STI）层堆叠的半导体衬底; 通过进行DSA以外的平版印刷图案化步骤，在所述基板的所述一侧上限定翅片区域，其中所述翅片结构将在所述翅片区域中产生; 以及使用DSA平版印刷图案，根据预定的散热片图案在散热片区域内的半导体衬底中制造翅片结构。 本公开还涉及相关联的半导体结构。

公开(公告)号：US20150243509A1

公开(公告)日：2015-08-27

申请号：US14628608

申请日：2015-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract translation: 在半导体衬底的区域中使用定向自组装（DSA）光刻图案来制造鳍结构的方法包括提供在其一侧上覆盖有浅沟槽隔离（STI）层堆叠的半导体衬底; 通过进行DSA以外的平版印刷图案化步骤，在所述基板的所述一侧上限定翅片区域，其中所述翅片结构将在所述翅片区域中产生; 以及使用DSA平版印刷图案，根据预定的散热片图案在散热片区域内的半导体衬底中制造翅片结构。 本公开还涉及相关联的半导体结构。

公开(公告)号：US20240234207A9

公开(公告)日：2024-07-11

申请号：US18486370

申请日：2023-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

公开(公告)号：US11824122B2

公开(公告)日：2023-11-21

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0669 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

公开(公告)号：US20230361205A1

公开(公告)日：2023-11-09

申请号：US18298820

申请日：2023-04-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Bilal Chehab ,  Julien Ryckaert

IPC: H01L29/775 ,  H01L27/085 ,  H01L29/423 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L29/775 ,  H01L27/085 ,  H01L29/42392 ,  H01L29/0673 ,  H01L23/5286

Abstract: A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.

公开(公告)号：US20230197831A1

公开(公告)日：2023-06-22

申请号：US18063991

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

IPC: H01L29/66

CPC classification number: H01L29/66553 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/42392

Abstract: A method is provided for forming a semiconductor device. The method includes: forming a device layer stack on a substrate, the device layer stack comprising a bottom sacrificial layer and an alternating sequence of upper sacrificial layers and channel layers; forming a sacrificial gate structure; etching through at least the upper sacrificial and channel layers of the device layer stack while using the sacrificial gate structure as an etch mask; forming a sacrificial spacer covering end surfaces of the upper sacrificial and channel layers; while the sacrificial spacer masks the end surfaces of the upper sacrificial and channel layers, further etching the device layer stack to remove the bottom sacrificial layer and thereby form a cavity in the device layer stack; forming a dielectric layer in the cavity, wherein forming the dielectric layer comprises depositing and then etching back a dielectric bottom material to a level below a bottom-most one of the channel layers; removing the sacrificial spacer; forming recesses and forming inner spacers in the recesses; and forming source and drain regions by epitaxially growing semiconductor material on the end surfaces of the channel layers.

公开(公告)号：US20230178630A1

公开(公告)日：2023-06-08

申请号：US18061065

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Naoto Horiguchi ,  Julien Ryckaert

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545

Abstract: A method for forming a FET device is provided. The method includes: forming a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers; etching each of first and second fin parts from each of first and second opposite sides of the fin structure such that a set of source cavities extending through the first fin part is formed in a first set of layers of the layer stack, and such that a set of drain cavities extending through the second fin part is formed in the first set of layers of the layer stack; filling the source and drain cavities with a dummy material; while masking the fin structure from the second side: removing the dummy material by etching from the first side, and subsequently, forming a source body and a drain body, each comprising a respective common body portion and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively; and while masking the fin structure from the first side: etching a third fin part from the second side such that a set of gate cavities extending through the third fin part is formed in a second set of layers, and subsequently, forming a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US11638391B2

公开(公告)日：2023-04-25

申请号：US17345827

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ruoyu Li ,  Stefan Kubicek ,  Julien Jussot

IPC: H10N60/01 ,  H10N60/10 ,  H10N60/83 ,  H10N69/00

Abstract: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

公开(公告)号：US11527431B2

公开(公告)日：2022-12-13

申请号：US17119802

申请日：2020-12-11

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Geert Mannaert

IPC: H01L21/762 ,  H01L21/8234

Abstract: According to an aspect of the disclosed technology, there is provided a method comprising: providing a substrate, the substrate supporting an STI-layer and a set of fin structures, each fin structure comprising an upper portion protruding above the STI-layer, forming a spacer layer over the upper portions of the set of fin structures and the STI-layer, forming a sacrificial layer over the spacer layer, the sacrificial layer at least partially embedding the upper portions of the fin structures, partially etching back the sacrificial layer to expose spacer layer portions above upper surfaces of the upper portions of the set of fin structures, and etching the spacer layer and exposing at least the upper surfaces of the upper portions of the set of fin structures, while the sacrificial layer at least partially masks spacer layer portions above the STI-layer.

公开(公告)号：US11430697B2

公开(公告)日：2022-08-30

申请号：US16843706

申请日：2020-04-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L21/033

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.