公开(公告)号：US20170372985A1

公开(公告)日：2017-12-28

申请号：US15191989

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53228 ,  H01L23/53238 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.

公开(公告)号：US09543260B2

公开(公告)日：2017-01-10

申请号：US13958276

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

Abstract translation: 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US09530720B2

公开(公告)日：2016-12-27

申请号：US14834846

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

公开(公告)号：US09269807B2

公开(公告)日：2016-02-23

申请号：US14716200

申请日：2015-05-19

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7816 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

公开(公告)号：US20150255597A1

公开(公告)日：2015-09-10

申请号：US14716200

申请日：2015-05-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/7816 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

Abstract translation: 半导体器件包括在半导体本体的第一区域中的漂移区域。 漂移区域包括第一导电类型的掺杂剂。 至少在漂移区域的边缘附近形成掺杂剂延迟区域。 将第二导电类型的掺杂剂注入半导体本体。 将半导体体进行退火以形成体区，使得第二导电类型的掺杂剂以第一扩散速率被驱动到半导体本体中。 掺杂剂延迟区域防止掺杂剂以第一扩散速率扩散到漂移区域。

公开(公告)号：US20130267093A1

公开(公告)日：2013-10-10

申请号：US13830185

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层未沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US20250159917A1

公开(公告)日：2025-05-15

申请号：US19025359

申请日：2025-01-16

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H10D30/01 ,  H01L21/02 ,  H01L21/78 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85 ,  H10D64/23

Abstract: A semiconductor device includes a plurality of mesas, each mesa including an epitaxial Group III nitride-based multi-layer structure, an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix, and a metallization structure including a gate finger and a drain finger arranged on the top surface of each mesa, a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa.

公开(公告)号：US12278275B2

公开(公告)日：2025-04-15

申请号：US18093434

申请日：2023-01-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

公开(公告)号：US12230689B2

公开(公告)日：2025-02-18

申请号：US17145507

申请日：2021-01-11

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.

公开(公告)号：US20240258382A1

公开(公告)日：2024-08-01

申请号：US18442743

申请日：2024-02-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.