公开(公告)号：US08987065B2

公开(公告)日：2015-03-24

申请号：US14090461

申请日：2013-11-26

Applicant: Intel Corporation

Inventor： Ravi K. Nailla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US12107042B2

公开(公告)日：2024-10-01

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/05 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20230197697A1

公开(公告)日：2023-06-22

申请号：US17552581

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  John S. Guzek ,  Hamid Azimi

IPC: H01L25/16 ,  H01L23/15 ,  H01L23/498 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L23/15 ,  H01L23/49827 ,  H01L28/60 ,  H01L23/49811 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate, having a surface, including a through-glass-substrate via (TGV) and a cavity on the surface; a first die nested in the cavity; an insulating material on the surface of the glass substrate; a first conductive pillar and a second conductive pillar through the insulating material; a capacitor, in the insulating material, including a first conductive layer, on the surface of the glass substrate, electrically coupled to the TGV and the first conductive pillar forming a first plate of the capacitor, a dielectric layer on the first conductive layer; and a second conductive layer, on the dielectric layer, electrically coupled to the second conductive pillar forming a second plate of the capacitor; and a second die, on the insulating material, electrically coupled to the first die.

公开(公告)号：US20220172962A1

公开(公告)日：2022-06-02

申请号：US17676565

申请日：2022-02-21

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US10930596B2

公开(公告)日：2021-02-23

申请号：US16327944

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： John S. Guzek

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L25/07 ,  H01L25/065 ,  H01L23/48 ,  H01L23/31

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

公开(公告)号：US10796988B2

公开(公告)日：2020-10-06

申请号：US16002740

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L23/52 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L25/18

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20200273721A1

公开(公告)日：2020-08-27

申请号：US16871503

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US10651051B2

公开(公告)日：2020-05-12

申请号：US15726008

申请日：2017-10-05

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US10083936B2

公开(公告)日：2018-09-25

申请号：US15289058

申请日：2016-10-07

Applicant: INTEL CORPORATION

Inventor： Weng Hong Teh ,  John S. Guzek ,  Shan Zhong

IPC: H01L25/065 ,  H01L23/12 ,  H01L23/498 ,  H01L23/13 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

公开(公告)号：US20180033648A1

公开(公告)日：2018-02-01

申请号：US15726008

申请日：2017-10-05

Applicant: Intel Corporation

Inventor： Robert L Sankman ,  John S. Guzek

IPC: H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/16 ,  H01L21/683 ,  H01L21/3105 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L23/00 ,  H01L21/50 ,  H01L21/78

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.