公开(公告)号：US08962354B2

公开(公告)日：2015-02-24

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66 ,  H01L49/02 ,  C23C14/22 ,  C23C16/455 ,  H01L29/51

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20150010705A1

公开(公告)日：2015-01-08

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L49/02 ,  C23C16/455 ,  H01L29/51 ,  C23C14/22

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20140361236A1

公开(公告)日：2014-12-11

申请号：US14467902

申请日：2014-08-25

Applicant: Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  Pragati Kumar ,  Prashant B. Phatak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.

Abstract translation: 描述用于形成非易失性电阻式切换存储器的ALD处理技术。 在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成 所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

公开(公告)号：US20140264239A1

公开(公告)日：2014-09-18

申请号：US13974278

申请日：2013-08-23

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括设置在两个较高带隙电介质层之间的低带隙电介质层。 高带隙电介质层可以掺杂掺杂材料以在高于存储器件的工作电压的能级下形成阱。

公开(公告)号：US20140179033A1

公开(公告)日：2014-06-26

申请号：US13727237

申请日：2012-12-26

Applicant: INTERMOLECULAR, INC.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20140175603A1

公开(公告)日：2014-06-26

申请号：US13722885

申请日：2012-12-20

Applicant: INTERMOLECULAR, INC.

Inventor： Venkat Ananthan ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L49/02

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L28/40 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP器件，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP器件与肖特基二极管相比可以具有更低的热量预算，并且可控制的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括夹在具有不同功函数值的两个电极之间的低缺陷电介质层，高缺陷电介质层。

公开(公告)号：US20140151626A1

公开(公告)日：2014-06-05

申请号：US13693820

申请日：2012-12-04

Applicant: INTERMOLECULAR INC.

Inventor： Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/32055 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP二极管，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP二极管可以具有比肖特基二极管更低的热预算和可控的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括阻挡层高度改性层，低漏电介质层和高泄漏电介质层。 这些层可以夹在两个电极之间。

公开(公告)号：US08698121B2

公开(公告)日：2014-04-15

申请号：US13935388

申请日：2013-07-03

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak ,  Tony P. Chiang ,  Michael Miller ,  Wen Wu

IPC: H01L47/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa.

Abstract translation: 描述了一种电阻式开关存储器，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特（eV）之间的金属氧化物 在第一电极和第二电极之间，金属氧化物层使用单极或双极开关电压进行大量介导的开关，用于从低电阻状态切换到高电阻状态，反之亦然。

公开(公告)号：US20130285695A1

公开(公告)日：2013-10-31

申请号：US13932640

申请日：2013-07-01

Applicant: Intermolecular, Inc.

Inventor： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: G01R31/28

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

公开(公告)号：US08531868B2

公开(公告)日：2013-09-10

申请号：US13720448

申请日：2012-12-19

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Prashant B. Phatak ,  Tony P. Chiang

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.