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    PRECISION TRENCH CAPACITOR
    51.
    发明申请
    PRECISION TRENCH CAPACITOR 有权
    精密电容电容器

    公开(公告)号：US20150303191A1

    公开(公告)日：2015-10-22

    申请号：US14257143

    申请日：2014-04-21

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

    IPC: H01L27/07 ,  H01L29/94 ,  H01L29/66

    CPC classification number: H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

    Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

    Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。

    SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR
    52.
    发明申请
    SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR 有权
    选择性的本地金属层形成用于改进的电化学行为

    公开(公告)号：US20150255328A1

    公开(公告)日：2015-09-10

    申请号：US14721440

    申请日：2015-05-26

    Applicant: International Business Machines Corporation

    Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

    Abstract translation: 一种形成集成电路器件的布线结构的方法包括在层间电介质（ILD）层内形成第一金属线，并在与第一金属线相邻的ILD层中形成第二金属线; 掩蔽所述第一和第二金属线的选定区域; 以周期性间隔选择性地在第一和第二金属线的暴露区域上电镀金属帽区域，使得单个金属线的相邻金属帽区域之间的间隔对应于临界长度L，在该临界长度L处，背应力梯度平衡电迁移力 在各个金属线上，以抑制电子的质量传递; 并且其中所述第一金属线的金属帽区域沿着共同的纵向轴线相对于所述第二金属线的金属帽区域以交错位置形成。

    Embedded on-chip security
    54.
    发明授权
    Embedded on-chip security 有权
    嵌入式片上安全性

    公开(公告)号：US09117824B2

    公开(公告)日：2015-08-25

    申请号：US14032218

    申请日：2013-09-20

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/00

    CPC classification number: H01L21/76802 ,  G06F21/73 ,  G09C1/00 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/564 ,  H01L23/57 ,  H01L2924/0002 ,  H03K19/003 ,  H03K19/0948 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

    Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

    Abstract translation: 本发明的实施例包括一种半导体结构，其包含用于实现物理不可克隆功能（PUF）的线性随机图案化互连结构的后端，用于形成半导体器件的方法以及用于使互连结构实现物理不可克隆功能的电路 。 该方法包括在衬底上形成半导体衬底和介电层。 随机图案化的互连结构形成在电介质层中。 互连结构的随机图案用于实现物理不可克隆功能，并且是在半导体结构的制造期间发生缺陷的结果。 该电路包括n沟道和p沟道金属氧化物半导体场效应晶体管（MOSFET）和随机图案化的互连结构，其作为MOSFET之间的电连接。 MOSFET之间的随机电气连接用于产生用于诸如认证或识别之类目的的唯一密钥。

    VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
    55.
    发明申请
    VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR 有权
    用于半导体的电压驱动智能特征晶体管

    公开(公告)号：US20150185277A1

    公开(公告)日：2015-07-02

    申请号：US14659793

    申请日：2015-03-17

    Applicant: International Business Machines Corporation

    Inventor： Charles J. Montrose ,  Ping-Chuan Wang

    IPC: G01R31/28 ,  G01R31/26

    CPC classification number: G01R31/2834 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31924 ,  G01R31/31935

    Abstract: A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

    Abstract translation: 一种用于测试半导体器件的方法，并形成相关系统。 提供驱动器通道，每个驱动器通道经由总线连接到存储设备并连接到相应的半导体器件。 每个驱动器通道包括：连接到相应半导体器件并且具有用于各个半导体器件的第一输入的第一电压驱动器，连接到相应的半导体器件并且具有用于各个半导体器件的第二输入的第二电压驱动器，第一和第二 分别在第一和第二电压驱动器中的光开关组和微控制器。 各个半导体器件与第一和第二电压驱动器之间的所有连接都响应于第一组光开关和第二组光开关的所有光开关而闭合。 使用驱动器通道和测试参数测试半导体器件。 将测试结果提供给存储设备。

    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH
    57.
    发明申请
    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH 有权
    通过深度通过硅片进行在线测量

    公开(公告)号：US20140332973A1

    公开(公告)日：2014-11-13

    申请号：US13889374

    申请日：2013-05-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hanyi Ding ,  J. Edwin Hostetter, JR. ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC: H01L21/66

    CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。

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