公开(公告)号：US09865598B1

公开(公告)日：2018-01-09

申请号：US15450725

申请日：2017-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0924 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823821 ,  H01L21/823878

Abstract: Disclosed herein are processes and structures for uniform STI recessing. A method of making a semiconductor device includes initially forming a dense region of at least two fins on a substrate. The fins have a hard mask layer on a surface. The dense region with the fins is adjacent to an isolated region without fins within a distance of a pitch of the fins. An oxide is deposited on the dense and isolated regions. The oxide is polished, stopping on the hard mask layer on the fins, and removing more oxide in the isolated region. Polishing results in forming a non-uniform oxide surface. The hard mask layer is removed from the fins. An etch process is performed to further recess the oxide in the dense and isolated regions, such that a thickness of the oxide in the dense region and the isolated region is substantially uniform.

公开(公告)号：US09859174B1

公开(公告)日：2018-01-02

申请号：US15191828

申请日：2016-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/033 ,  H01L27/12 ,  H01L21/28 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823456 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/66545

Abstract: A semiconductor device comprises a source/drain region arranged on a substrate and a first gate stack having a first length arranged on a first channel region of the substrate. A second gate stack having a second length is arranged on a second channel region of the substrate. The first length is greater than the second length.

公开(公告)号：US20170104062A1

公开(公告)日：2017-04-13

申请号：US14880659

申请日：2015-10-12

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/0676 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

公开(公告)号：US11495688B2

公开(公告)日：2022-11-08

申请号：US17197477

申请日：2021-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Peng Xu ,  Zhenxing Bi

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/417

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

公开(公告)号：US11489044B2

公开(公告)日：2022-11-01

申请号：US17134667

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Yi Song ,  Lijuan Zou

IPC: H01L29/06 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

公开(公告)号：US11453911B2

公开(公告)日：2022-09-27

申请号：US16841866

申请日：2020-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: B82Y30/00 ,  C12Q1/6869 ,  G01N33/487 ,  G01N27/447 ,  B81B1/00 ,  B81C1/00

Abstract: A method for fabricating a stacked nanopore includes forming a stack of layers having alternating conductive lines and dielectric layers on a substrate, and patterning the stack to form a staircase structure with the conductive lines having a length gradually changing at each level in the stack. The method also includes depositing and planarizing a dielectric material over the staircase structure, forming contacts through the dielectric material to the conductive lines for each level of conductive lines, etching a nanopore through the stack of layers to form pairs of opposing electrodes across the nanopore using the conductive lines; and opening up the substrate to expose the nanopore.

公开(公告)号：US11302797B2

公开(公告)日：2022-04-12

申请号：US16799237

申请日：2020-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Thamarai S. Devarajan ,  Balasubramanian Pranatharthiharan ,  Sanjay C. Mehta ,  Muthumanickam Sankarapandian

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：US11158730B2

公开(公告)日：2021-10-26

申请号：US15959458

申请日：2018-04-23

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

公开(公告)号：US20210288184A1

公开(公告)日：2021-09-16

申请号：US17197477

申请日：2021-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Peng Xu ,  Zhenxing Bi

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

公开(公告)号：US11056399B2

公开(公告)日：2021-07-06

申请号：US16380487

申请日：2019-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yao Yao ,  Andrew M. Greene ,  Veeraraghavan S. Basker ,  Kangguo Cheng ,  Zhenxing Bi ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.