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公开(公告)号：US20240105606A1
公开(公告)日：2024-03-28
申请号：US17935138
申请日：2022-09-26
IPC分类号： H01L23/528 , H01L21/02 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L23/5286 , H01L21/02532 , H01L21/02603 , H01L21/28123 , H01L21/823807 , H01L21/823871 , H01L21/823878 , H01L27/092 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.
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公开(公告)号：US20240105590A1
公开(公告)日：2024-03-28
申请号：US17951739
申请日：2022-09-23
IPC分类号： H01L23/522 , H01L21/768 , H01L21/84 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76819 , H01L21/845 , H01L23/5283 , H01L23/5286 , H01L23/53295
摘要： Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.
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公开(公告)号：US20240071904A1
公开(公告)日：2024-02-29
申请号：US17897876
申请日：2022-08-29
发明人： Chanro Park , Koichi Motoyama , Yann Mignot , Hsueh-Chung Chen
IPC分类号： H01L23/522 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/31122 , H01L21/76807 , H01L21/76831 , H01L21/76846 , H01L21/76871 , H01L23/5283 , H01L23/53238 , H01L23/5329
摘要： A microelectronics structure including a skip level via extending from an upper level metal line in an upper level of the at least two interlevel dielectric levels through a first an interlevel dielectric level that is on the substrate level without contacting an interlevel metal line. The skip level via extends into electrical contact with a first element of electrical contact features in a lower level of the at least two interlevel dielectric levels. The skip level via includes a spacer that is present on sidewalls of the skip level via. The structure also includes a single level via, in which the dielectric material of the spacer of the skip level via is not present on the sidewalls of the single level via.
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公开(公告)号：US20240038547A1
公开(公告)日：2024-02-01
申请号：US17873674
申请日：2022-07-26
发明人： Chanro Park , Koichi Motoyama , Hsueh-Chung Chen , Yann Mignot
IPC分类号： H01L21/3213 , H01L23/528 , H01L21/033
CPC分类号： H01L21/32139 , H01L23/528 , H01L21/0337 , H01L21/0332 , H01L21/7684
摘要： A substrative patterning process is provided that forms an interconnect structure including a connector tab located between two adjacent electrically conductive line structures. The connector tab and the two adjacent electrically conductive line structures are of unitary construction and are located in a same metallization level.
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公开(公告)号：US11848264B2
公开(公告)日：2023-12-19
申请号：US17303600
申请日：2021-06-03
IPC分类号： H01L23/522 , H01L23/532 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/7685 , H01L21/76852 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53257 , H01L23/53266
摘要： A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.
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公开(公告)号：US20230389434A1
公开(公告)日：2023-11-30
申请号：US17804795
申请日：2022-05-31
CPC分类号： H01L43/12 , H01L43/02 , H01L43/10 , H01L43/08 , G11C11/161 , H01L27/222
摘要： A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.
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公开(公告)号：US20230187341A1
公开(公告)日：2023-06-15
申请号：US17546682
申请日：2021-12-09
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76834 , H01L21/76832 , H01L21/76877 , H01L23/53295
摘要： An electrical communication structure that includes a plurality of metal line levels, a first metal line in a first metal line level of the plurality of line levels, and a second metal line in an upper metal line level of the plurality of line levels. A base of the second metal line is atop a metal etch stop layer that is aligned with edges of the second metal line. The electrical communication structure further includes a via that extends from the first metal line to the second metal line through the plurality of line levels. the via is not in electrical communication with at least one an intermediate metal line within the plurality of line levels between the first metal line level and the upper metal line level. The via has a metal fill that is in direct contact with a metal fill of the first metal line.
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公开(公告)号：US20230187278A1
公开(公告)日：2023-06-15
申请号：US17551998
申请日：2021-12-15
发明人： CHANRO PARK , Koichi Motoyama , Hsueh-Chung Chen
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76897 , H01L23/5226
摘要： An interconnect structure that in one embodiment can include a first metal line level having a first metal line, a second metal line level having a second metal line, and a via line level present between the first and second metal line levels. The via line level includes a via interlevel dielectric surrounding a via stack. The via stack may include an interface metal portion that is in contact with the first metal line, a via intralevel dielectric on the interface metal portion, and a cap metal portion in contact with the second metal line and extending through the via intralevel dielectric into contact with the interface metal portion. In some embodiments, the length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack.
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公开(公告)号：US20230178421A1
公开(公告)日：2023-06-08
申请号：US17544136
申请日：2021-12-07
发明人： Chanro Park , Koichi Motoyama , Hsueh-Chung Chen , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76807 , H01L21/76885 , H01L21/7688 , H01L23/5226
摘要： Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The methods may include forming a subtractive line from a bottom metal layer and a sacrificial hard mask above the bottom metal layer, depositing a scaffolding material around the subtractive line, forming a via mask over a via portion of the sacrificial hard mask and the scaffolding material, etching the sacrificial hard mask that is not covered by the via mask, to form a sacrificial via, removing the via mask and the scaffolding material, depositing a low-κ layer around the subtractive line and the sacrificial via, removing the sacrificial via to form a via hole within the low-κ layer, and forming a top via by metallizing the via hole.
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公开(公告)号：US20230177247A1
公开(公告)日：2023-06-08
申请号：US17542882
申请日：2021-12-06
IPC分类号： G06F30/3953 , G06F30/398
CPC分类号： G06F30/3953 , G06F30/398 , G06F2119/02
摘要： A computer-implemented method of assessing roughness in metallic lines of an integrated circuit (IC) is provided. The computer-implemented method includes developing a library of roughness characterizations for metal lines of varying characteristics and dimensions. The computer-implemented method further includes fabricating a testable IC and identifying, in the testable IC, a location of interest (LoI) at which roughness of a metal line within the LoI could impact IC performance. Also, the computer-implemented method includes developing, from the library, a roughness model using the roughness characterizations for those metal lines having characteristics and dimensions corresponding to those of the metal line within the LoI and refining the library and the roughness model based on a comparison of the roughness model and an actual roughness of the metal line within the LoI to obtain a final roughness model.
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