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    FINFET DIODE WITH INCREASED JUNCTION AREA
    51.
    发明申请
    FINFET DIODE WITH INCREASED JUNCTION AREA 失效
    FINFET二极管与增加的连接区域

    公开(公告)号：US20130285208A1

    公开(公告)日：2013-10-31

    申请号：US13456921

    申请日：2012-04-26

    申请人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    IPC分类号： H01L29/861 ,  H01L21/329

    CPC分类号： H01L29/861 ,  H01L21/845 ,  H01L27/0266 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6609 ,  H01L29/785

    摘要： A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

    摘要翻译： 公开了一种FinFET二极管及其制造方法。 在一个实施例中，二极管包括半导体衬底，设置在半导体衬底上的绝缘体层，设置在绝缘体层上的第一硅层，形成在第一硅层的二极管部分中的多个鳍片。 第一硅层的区域设置成与多个翅片中的每一个相邻。 第二硅层设置在形成在第一硅层的二极管部分中的多个翅片上。 栅极环设置在第一硅层上。 门环布置成闭合形状，并且包围形成在第一硅层的二极管部分中的多个翅片的一部分。

    Method and structure for low resistive source and drain regions in a replacement metal gate process flow
    53.
    发明授权
    Method and structure for low resistive source and drain regions in a replacement metal gate process flow 有权
    替代金属栅极工艺流程中低电阻源极和漏极区域的方法和结构

    公开(公告)号：US08432002B2

    公开(公告)日：2013-04-30

    申请号：US13170565

    申请日：2011-06-28

    申请人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/72

    CPC分类号： H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric and a metal gate are then formed into the extended opening.

    摘要翻译： 在一个实施例中，提供了一种方法，其包括提供包括其中位于其中的至少一个器件区域的半导体衬底的结构以及位于所述至少一个器件区域中的半导体衬底的上表面上的掺杂半导体层。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物的牺牲栅极区。 然后形成平坦化电介质材料，去除牺牲栅极区域以形成露出掺杂半导体层的一部分的开口。 开口延伸到半导体衬底的上表面，然后执行退火，其导致掺杂剂的剩余部分在掺杂半导体层的剩余部分中形成源区域和漏极区域，半导体衬底的位于第 掺杂半导体层的剩余部分。 然后，将高k栅极电介质和金属栅极形成为延伸的开口。

    Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow
    54.
    发明申请
    Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow 有权
    替代金属栅极工艺流程中低电阻源极和漏极区域的方法和结构

    公开(公告)号：US20130001706A1

    公开(公告)日：2013-01-03

    申请号：US13170565

    申请日：2011-06-28

    申请人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric and a metal gate are then formed into the extended opening.

    摘要翻译： 在一个实施例中，提供了一种方法，其包括提供包括其中位于其中的至少一个器件区域的半导体衬底的结构以及位于所述至少一个器件区域中的半导体衬底的上表面上的掺杂半导体层。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物的牺牲栅极区。 然后形成平坦化电介质材料，去除牺牲栅极区域以形成露出掺杂半导体层的一部分的开口。 开口延伸到半导体衬底的上表面，然后执行退火，其导致掺杂剂的剩余部分在掺杂半导体层的剩余部分中形成源区域和漏极区域，半导体衬底的位于第 掺杂半导体层的剩余部分。 然后，将高k栅极电介质和金属栅极形成为延伸的开口。

    Bulk fin-field effect transistors with well defined isolation
    57.
    发明授权
    Bulk fin-field effect transistors with well defined isolation 有权
    散装场效应晶体管具有明确的隔离

    公开(公告)号：US08420459B1

    公开(公告)日：2013-04-16

    申请号：US13277956

    申请日：2011-10-20

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

    摘要： A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

    摘要翻译： 通过在半导体衬底上形成虚拟鳍结构制造的鳍状场效晶体管。 在半导体衬底上形成电介质层。 电介质层围绕虚拟翅片结构。 去除虚拟翅片结构以在电介质层内形成空腔。 空腔暴露半导体衬底的一部分，从而在腔内形成半导体衬底的暴露部分。 将掺杂剂注入到空腔内的半导体衬底的暴露部分中，从而在腔内形成掺杂剂注入的半导体衬底的暴露部分。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。

    MOSFET INCLUDING ASYMMETRIC SOURCE AND DRAIN REGIONS
    58.
    发明申请
    MOSFET INCLUDING ASYMMETRIC SOURCE AND DRAIN REGIONS 失效
    MOSFET包括不对称源和漏极区

    公开(公告)号：US20130049115A1

    公开(公告)日：2013-02-28

    申请号：US13216554

    申请日：2011-08-24

    申请人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    Low resistance source and drain extensions for ETSOI
    59.
    发明授权
    Low resistance source and drain extensions for ETSOI 失效
    用于ETSOI的低电阻源和漏极扩展

    公开(公告)号：US08614486B2

    公开(公告)日：2013-12-24

    申请号：US13605260

    申请日：2012-09-06

    申请人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    发明人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    IPC分类号： H01L29/02 ,  H01L21/02

    CPC分类号： H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

    摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

    摘要翻译： 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。