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115 条记录 (耗时 0.023 秒)

    Method of patterning elements within a semiconductor topography
    51.
    发明授权
    Method of patterning elements within a semiconductor topography 有权
    半导体形貌图案化元件的方法

    公开(公告)号：US07390750B1

    公开(公告)日：2008-06-24

    申请号：US11087924

    申请日：2005-03-23

    申请人： Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

    发明人： Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132

    摘要： A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

    摘要翻译： 提供了一种方法，其包括形成与半导体形貌的图案化牺牲结构相邻的硬掩模特征，选择性地去除图案化的牺牲结构以暴露下层并蚀刻与硬掩模特征对准的下层的暴露部分。 在一些实施例中，形成硬掩模特征可以包括在图案化的牺牲结构和下层之上顺应地沉积硬掩模材料，以及橡皮布蚀刻硬掩模材料，使得图案化的牺牲结构的上表面和下层的部分被暴露， 硬掩模材料保留在图案化牺牲结构的侧壁上。 该方法可以应用于产生包括多个栅极结构的示例性半导体形貌，每个栅极结构的宽度小于约70nm，其中多个栅极结构之间的宽度变化小于约10％。

    Stress liner for integrated circuits
    52.
    发明授权
    Stress liner for integrated circuits 有权
    集成电路应力衬垫

    公开(公告)号：US07384833B2

    公开(公告)日：2008-06-10

    申请号：US11350160

    申请日：2006-02-07

    申请人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

    发明人： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

    摘要翻译： 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    53.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07256087B1

    公开(公告)日：2007-08-14

    申请号：US11018422

    申请日：2004-12-21

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。

    Protection of low-k dielectric in a passivation level
    55.
    发明授权
    Protection of low-k dielectric in a passivation level 有权
    保护低k电介质在钝化水平

    公开(公告)号：US07192867B1

    公开(公告)日：2007-03-20

    申请号：US10184336

    申请日：2002-06-26

    申请人： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

    发明人： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76831 ,  H01L21/76814

    摘要： In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

    摘要翻译： 在一个实施例中，钝化层包括低k电介质。 为了防止低k电介质暴露于空气时吸收水分，低k电介质的暴露部分被间隔物覆盖。 可以理解，这有助于低k电介质在钝化层中的集成。 钝化层中的低k电介质有助于降低金属线路上的电容，从而减少RC延迟并增加信号传播速度。

    Method for controlling the oxidation of implanted silicon
    58.
    发明授权
    Method for controlling the oxidation of implanted silicon 失效
    控制植入硅氧化的方法

    公开(公告)号：US06555484B1

    公开(公告)日：2003-04-29

    申请号：US08878728

    申请日：1997-06-19

    申请人： Krishnaswamy Ramkumar ,  Hanna Bamnolker

    发明人： Krishnaswamy Ramkumar ,  Hanna Bamnolker

    IPC分类号： H01L21265

    CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/2822 ,  Y10S438/911 ,  Y10S438/92 ,  Y10S438/981

    摘要： Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.

    摘要翻译： 用掺杂剂/离子注入半导体衬底的两个不同区域。 注入可以通过设置在衬底上的牺牲氧化层发生。 在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。 然后在衬底的注入区域上生长氧化物层。 对于一些实施例，衬底可以用砷和/或磷进行注入。 此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

    Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation
    59.
    发明授权
    Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation 失效
    基于使用倾斜Si蚀刻和干场氧化的凹陷区域的隔离方案

    公开(公告)号：US6033991A

    公开(公告)日：2000-03-07

    申请号：US939838

    申请日：1997-09-29

    申请人： Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

    发明人： Krishnaswamy Ramkumar ,  Pamela Trammel ,  Sharmin Sadoughi

    IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

    CPC分类号： H01L21/76202 ,  H01L21/7621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31662

    摘要： A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.

    摘要翻译： 在半导体管芯中形成场氧化物或隔离区域的方法。 对氧化掩模层（位于衬底上方的氧化物层上方）进行构图并随后进行蚀刻，优选地使得氧化掩模层可具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氧化掩模层的侧壁具有倾斜表面的凹部。 然后使用干燥的氧化气氛将场氧化物生长在凹槽中。 衬底凹槽的倾斜侧壁有效地将暴露的衬底的表面远离氧化掩模层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀减少和较少的场氧化物稀化。 衬底侧壁的斜率的优选范围相对于氧化掩模层侧壁约为10°至40°。