公开(公告)号：US20150357209A1

公开(公告)日：2015-12-10

申请号：US14827052

申请日：2015-08-14

Applicant: Lam Research Corporation

Inventor： Alexei Marakhtanov ,  Mirzafer K. Abatchev ,  Rajinder Dhindsa ,  Eric Hudson ,  Andrew D. Bailey, III

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/311

CPC classification number: H01L21/67069 ,  C23C14/345 ,  C23C16/505 ,  H01J37/32091 ,  H01J37/32137 ,  H01J2237/334 ,  H01J2237/3343 ,  H01J2237/3348 ,  H01L21/3065 ,  H01L21/31116 ,  H01L22/20 ,  H05H2001/4675

Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.

Abstract translation: 提供了在电容耦合等离子体室中用于半导体处理的装置，方法和计算机程序。 腔室包括底部射频（RF）信号发生器，顶部RF信号发生器和RF相位控制器。 底部RF信号发生器耦合到室中的底部电极，并且顶部RF信号发生器耦合到顶部电极。 此外，底部RF信号被设置在第一相位，并且顶部RF信号被设置在第二阶段。 RF相位控制器可操作以接收底部RF信号并且可操作以设置第二相位的值。 此外，RF相位控制器可操作以跟踪第一相位和第二相位，以保持最大RF信号的最大值与底部RF信号的最小值之间的时间差大约为预定的常数值，导致增加 到晶片表面的负离子通量。

公开(公告)号：US09039911B2

公开(公告)日：2015-05-26

申请号：US13626793

申请日：2012-09-25

Applicant: Lam Research Corporation

Inventor： Eric A. Hudson ,  Andrew D. Bailey, III ,  Rajinder Dhindsa

IPC: B44C1/22 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32192 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32458 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67069

Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.

Abstract translation: 用于蚀刻具有至少一个初级等离子体产生区域的等离子体处理室中的衬底和通过半屏障结构从所述初级等离子体产生区域分离的次级等离子体产生区域的方法。 该方法包括从主要等离子体产生区域中的主进料气体产生主要等离子体。 该方法还包括从次级等离子体产生区域中的二次进料气体产生二次等离子体，以使至少一些来自第二等离子体的物质迁移到初级等离子体产生区域。 该方法另外包括在初级等离子体已经用来自二次等离子体的迁移物质增强之后用初级等离子体蚀刻基板。

公开(公告)号：US08470126B2

公开(公告)日：2013-06-25

申请号：US13629129

申请日：2012-09-27

Applicant: Lam Research Corporation

Inventor： Ben-Li Sheu ,  Rajinder Dhindsa ,  Vinay Pohray ,  Eric A. Hudson ,  Andrew D. Bailey, III

IPC: C23C16/52 ,  C23C16/50 ,  C23C16/503 ,  C23F1/00 ,  H01L21/306 ,  G05B15/00 ,  G06F17/00 ,  C23C16/06 ,  C23C16/22

CPC classification number: H01L21/31116 ,  H01L21/31144

Abstract: An apparatus for etching features in an etch layer is provided. A plasma processing chamber is provided, comprising a chamber wall, a chuck, a pressure regulator, an electrode or coil, a gas inlet, and a gas outlet. A gas source comprises a fluorine free deposition gas source and an etch gas source. A controller comprises at least one processor and computer readable media, comprising computer readable code for providing a conditioning for a patterned pseudo-hardmask, wherein the conditioning comprises computer readable code providing a fluorine free deposition gas comprising a hydrocarbon gas, computer readable code for forming a plasma, computer readable code for providing a bias less than 500 volts, and computer readable code for forming a deposition on top of the patterned pseudo-hardmask, computer readable code for etching the etch layer, and computer readable code for cyclically repeating the conditioning and etching at least twice.

Abstract translation: 提供了用于蚀刻蚀刻层中的特征的设备。 提供了等离子体处理室，其包括室壁，卡盘，压力调节器，电极或线圈，气体入口和气体出口。 气源包括无氟沉积气体源和蚀刻气体源。 控制器包括至少一个处理器和计算机可读介质，其包括用于为图案化伪硬掩模提供调节的计算机可读代码，其中所述调节包括提供包含烃气体的无氟沉积气体的计算机可读代码，用于形成的计算机可读代码 用于提供小于500伏特的偏置的等离子体，计算机可读代码以及用于在图案化伪硬掩模上形成沉积的计算机可读代码，用于蚀刻蚀刻层的计算机可读代码以及用于循环重复调节的计算机可读代码 并蚀刻至少两次。

公开(公告)号：US20130020026A1

公开(公告)日：2013-01-24

申请号：US13629129

申请日：2012-09-27

Applicant: Lam Research Corporation

Inventor： Ben-Li Sheu ,  Rajinder Dhindsa ,  Vinay Pohray ,  Eric A. Hudson ,  Andrew D. Bailey, III

IPC: H01L21/3065

CPC classification number: H01L21/31116 ,  H01L21/31144

Abstract: An apparatus for etching features in an etch layer is provided. A plasma processing chamber is provided, comprising a chamber wall, a chuck, a pressure regulator, an electrode or coil, a gas inlet, and a gas outlet. A gas source comprises a fluorine free deposition gas source and an etch gas source. A controller comprises at least one processor and computer readable media, comprising computer readable code for providing a conditioning for a patterned pseudo-hardmask, wherein the conditioning comprises computer readable code providing a fluorine free deposition gas comprising a hydrocarbon gas, computer readable code for forming a plasma, computer readable code for providing a bias less than 500 volts, and computer readable code for forming a deposition on top of the patterned pseudo-hardmask, computer readable code for etching the etch layer, and computer readable code for cyclically repeating the conditioning and etching at least twice.

Abstract translation: 提供了用于蚀刻蚀刻层中的特征的设备。 提供了等离子体处理室，其包括室壁，卡盘，压力调节器，电极或线圈，气体入口和气体出口。 气源包括无氟沉积气体源和蚀刻气体源。 控制器包括至少一个处理器和计算机可读介质，其包括用于为图案化伪硬掩模提供调节的计算机可读代码，其中所述调节包括提供包含烃气体的无氟沉积气体的计算机可读代码，用于形成的计算机可读代码 用于提供小于500伏特的偏置的等离子体，计算机可读代码以及用于在图案化伪硬掩模上形成沉积的计算机可读代码，用于蚀刻蚀刻层的计算机可读代码以及用于循环重复调节的计算机可读代码 并蚀刻至少两次。

公开(公告)号：US20230274911A1

公开(公告)日：2023-08-31

申请号：US18013477

申请日：2021-06-24

Applicant: Lam Research Corporation

Inventor： Andrew D. Bailey, III

IPC: H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/3266 ,  H01J37/32651 ,  H01J2237/3343 ,  H01J2237/184

Abstract: Methods, systems, apparatuses, and computer programs are presented for controlling etch rate and plasma uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber including a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor configured to detect a signal representing a residual magnetic field associated with the vacuum chamber. At least one magnetic field source is configured to generate one or more supplemental magnetic fields through the processing zone of the vacuum chamber. A magnetic field controller is coupled to the magnetic field sensor and the at least one magnetic field source. The magnetic field controller is configured to adjust at least one characteristic of the one or more supplemental magnetic fields, causing the one or more supplemental magnetic fields to reduce the residual magnetic field to a pre-determined value.

公开(公告)号：US11704463B2

公开(公告)日：2023-07-18

申请号：US17301345

申请日：2021-03-31

Applicant: Lam Research Corporation

Inventor： Ye Feng ,  Marcus Musselman ,  Andrew D. Bailey, III ,  Mehmet Derya Tetiker ,  Saravanapriyan Sriraman ,  Yan Zhang ,  Julien Mailfert

IPC: G06F30/367 ,  G03F1/36 ,  G03F1/78 ,  G03F1/86 ,  G03F1/80

CPC classification number: G06F30/367 ,  G03F1/36 ,  G03F1/78 ,  G03F1/80 ,  G03F1/86

Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

公开(公告)号：US11011353B2

公开(公告)日：2021-05-18

申请号：US15403786

申请日：2017-01-11

Applicant: LAM RESEARCH CORPORATION

Inventor： Marcus Musselman ,  Andrew D. Bailey, III ,  Jon McChesney

IPC: H01J37/32 ,  H01L21/687 ,  H01L21/68 ,  H01L21/67

Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller at least one of raises the edge ring to selectively cause the edge ring to engage the substrate and lowers the inner portion to selectively cause the edge ring to engage the substrate. The controller determines when the edge ring engages the substrate and calculates at least one characteristic of the substrate processing system based on the determination of when the edge ring engages the substrate.

公开(公告)号：US10997345B2

公开(公告)日：2021-05-04

申请号：US16741735

申请日：2020-01-13

Applicant: Lam Research Corporation

Inventor： Ye Feng ,  Marcus Musselman ,  Andrew D. Bailey, III ,  Mehmet Derya Tetiker ,  Saravanapriyan Sriraman ,  Yan Zhang ,  Julien Mailfert

IPC: G06F30/367 ,  G03F1/36 ,  G03F1/78 ,  G03F1/86 ,  G03F1/80

Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

公开(公告)号：US10763142B2

公开(公告)日：2020-09-01

申请号：US14860078

申请日：2015-09-21

Applicant: Lam Research Corporation

Inventor： Marcus Musselman ,  Juan Valdivia, III ,  Hua Xiang ,  Andrew D. Bailey, III ,  Yoko Yamaguchi ,  Qian Fu ,  Aaron Eppler

IPC: G05B19/418 ,  H01L21/67

Abstract: A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.

公开(公告)号：US10553399B2

公开(公告)日：2020-02-04

申请号：US15011112

申请日：2016-01-29

Applicant: Lam Research Corporation

Inventor： Alexei Marakhtanov ,  Rajinder Dhindsa ,  Eric Hudson ,  Andrew D. Bailey, III

IPC: H01J37/32 ,  H01L21/311 ,  H01L21/67

Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period.