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195 条记录 (耗时 0.036 秒)

    Semiconductor structures
    51.
    发明授权
    Semiconductor structures 有权
    半导体结构

    公开(公告)号：US07335935B2

    公开(公告)日：2008-02-26

    申请号：US11188235

    申请日：2005-07-22

    申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

    发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

    摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

    Intermediate semiconductor device having activated oxide-based layer for electroless plating
    55.
    发明授权
    Intermediate semiconductor device having activated oxide-based layer for electroless plating 有权
    具有用于无电镀的活性氧化物基层的中间半导体器件

    公开(公告)号：US07042010B2

    公开(公告)日：2006-05-09

    申请号：US11124068

    申请日：2005-05-06

    申请人： Nishant Sinha

    发明人： Nishant Sinha

    IPC分类号： H01L31/112

    CPC分类号： H01L21/76843 ,  H01L21/105 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/32134 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76874 ,  H01L27/10852 ,  H01L27/10897 ,  H01L28/65

    摘要： An intermediate semiconductor device that includes a semiconductor substrate and an oxide-based layer over the substrate. The oxide-based layer has an activated catalytic surface on at least one selected area thereof which is adapted for electroless plating. The intermediate may also include high aspect ratio capacitor containers, trenches, vias, and other openings whose surfaces can be made conductive by selectively electrolessly plating a metal or metal alloy thereon.

    摘要翻译： 一种中间半导体器件，其包括半导体衬底和在衬底上的基于氧化物的层。 氧化物基层在其至少一个选择区域上具有活化的催化表面，其适于化学镀。 中间体还可以包括高纵横比电容器容器，沟槽，通孔和其他开口，其表面可以通过在其上选择性地非电解电镀金属或金属合金而被导电。

    Filling plugs through chemical mechanical polish
    56.
    发明授权
    Filling plugs through chemical mechanical polish 失效
    通过化学机械抛光填充塞子

    公开(公告)号：US06969301B2

    公开(公告)日：2005-11-29

    申请号：US10866281

    申请日：2004-06-11

    申请人： Nishant Sinha

    发明人： Nishant Sinha

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L45/00 ,  H05K3/40 ,  B24B1/00

    CPC分类号： H01L21/76877 ,  H01L21/3212 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/1658 ,  H01L45/1683 ,  H05K3/4038 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, however the openings are not completely filled. A chemical mechanical polishing process using an alumina based slurry at a neutral or slightly basic pH and no oxidizer is used to smear the malleable conductive layer sufficiently to fill the remainder of the openings in the dielectric layer forming filled or substantially filled plugs.

    摘要翻译： 通过化学机械抛光填充塞子的方案包括在其上形成有开口的介电层上沉积可延展的导电层。 沉积有韧性的导电层，使得在开口内形成衬垫，然而开口未被完全填充。 使用在中性或轻微碱性pH下使用氧化铝基浆料并且不使用氧化剂的化学机械抛光方法来充分地涂抹可延展的导电层，以填充形成填充或基本上填充的塞子的电介质层中的其余开口。

    Activation of oxides for electroless plating
    59.
    发明授权
    Activation of oxides for electroless plating 失效
    化学镀氧化物的活化

    公开(公告)号：US06872659B2

    公开(公告)日：2005-03-29

    申请号：US10223315

    申请日：2002-08-19

    申请人： Nishant Sinha

    发明人： Nishant Sinha

    IPC分类号： H01L21/02 ,  H01L21/105 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/108 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/105 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/32134 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76874 ,  H01L27/10852 ,  H01L27/10897 ,  H01L28/65

    摘要： The present invention provides approaches for electroless deposition of conductive materials onto the surface of oxide-based materials, including nonconductive metal oxides, in a manner that does not require intervening conductive pastes, nucleation layers, or additional seed or activation layers formed over the surface of the oxide-based layer. According to one embodiment of the present invention, a layer of a titanium-based material is formed over an oxide-based surface. The layer of titanium-based material is subsequently removed from the surface of the oxide-based layer in a manner such that the surface of the oxide-based layer is activated for electroless deposition. A metal or metal alloy is then plated over the oxide-based surface using electroless plating techniques.

    摘要翻译： 本发明提供了将导电材料无电沉积到氧化物基材料（包括非导电金属氧化物）的表面上的方法，其方式不需要介入导电浆料，成核层或在其表面上形成的附加种子或活化层 氧化物层。 根据本发明的一个实施例，在氧化物基表面上形成钛基材料层。 随后以氧化物基层的表面激活以进行无电沉积的方式，从氧化物基层的表面去除钛基材料层。 然后使用化学镀技术将金属或金属合金镀在氧化物基表面上。

    Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
    60.
    发明申请
    Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias 有权
    用于制造导电部件，通孔和半导体部件的工艺和集成方案，包括导电贯通晶片通孔

    公开(公告)号：US20050064707A1

    公开(公告)日：2005-03-24

    申请号：US10668914

    申请日：2003-09-23

    申请人： Nishant Sinha

    发明人： Nishant Sinha

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44

    CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

    摘要翻译： 公开了一种在半导体部件中形成导电通孔的方法。 该方法包括提供具有第一表面和相对的第二表面的基底。 在基板上形成至少一个孔，该孔在第一表面和相对的第二表面之间延伸。 种子层形成在限定基底的至少一个孔并且涂覆有导电层的侧壁上，并且导电或非导电填充材料被引入至少一个孔内的剩余空间中。 还公开了使用盲孔通过基板形成导电通孔的方法。 还公开了具有包括本发明的导电通孔的基板的半导体元件和电子系统。