公开(公告)号：US09093462B2

公开(公告)日：2015-07-28

申请号：US13887723

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian M. Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L23/48 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20140225246A1

公开(公告)日：2014-08-14

申请号：US14133451

申请日：2013-12-18

Applicant: QUALCOMM INCORPORATED

Inventor： Brian Matthew Henderson ,  Durodami Joscelyn Lisk ,  Shiqun Gu ,  Ratibor Radojcic ,  Matthew Michael Nowak

IPC: H01L23/538 ,  H01L23/36

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5286 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.

Abstract translation: 一些实施方案提供了集成器件，其包括第一衬底，耦合到第一衬底的第一裸片，耦合到第一裸片的第二裸片以及耦合到第二裸片的第二衬底。 第二基板被配置为提供用于到第二管芯的信号的电路径。 集成装置还包括围绕第一管芯和第二管芯的模制件以及耦合到第二衬底的多个通孔模具通孔（TMV）。 TMV被配置为提供通过第二基板的信号到第二管芯的电路径。 在一些实施方案中，第二衬底包括被配置为向第二裸片提供信号的电路的信号分配结构。 在一些实施方案中，第一衬底和第二衬底是向第二裸片提供信号的信号分配网络的一部分。

公开(公告)号：US10944379B2

公开(公告)日：2021-03-09

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Shiqun Gu ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim

IPC: H03H9/05 ,  H03H9/64 ,  H03H3/08 ,  H03H9/72 ,  H03H9/70 ,  H03H3/02

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

公开(公告)号：US10312193B2

公开(公告)日：2019-06-04

申请号：US15235790

申请日：2016-08-12

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Chengjie Zuo ,  Steve Fanelli ,  Husnu Ahmet Masaracioglu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/66 ,  H01L25/07 ,  H01L25/00 ,  H03H1/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the secod encapsulation layer at least partially encapsulates the second plurality of filters.

公开(公告)号：US10271745B2

公开(公告)日：2019-04-30

申请号：US15186347

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Kenneth Kaskoun ,  Eugene Dantsker ,  Russel Allyn Martin

IPC: A61B5/1455 ,  A61B5/024 ,  A61B5/145 ,  A61B5/00

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

公开(公告)号：US10163771B2

公开(公告)日：2018-12-25

申请号：US15231512

申请日：2016-08-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L25/00 ,  H01L27/092 ,  H01L49/02 ,  H01L23/48

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

公开(公告)号：US10141908B2

公开(公告)日：2018-11-27

申请号：US15240987

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil Mudakatte ,  David Francis Berdy ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Shiqun Gu ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H1/00 ,  H03H7/01 ,  H03H7/46 ,  H01L49/02 ,  H05K1/16 ,  H05K1/03

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：US10103135B2

公开(公告)日：2018-10-16

申请号：US15275068

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu

IPC: H01L27/01 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/552 ,  H03H7/01 ,  H03H7/46 ,  H04B1/00 ,  H01L23/00

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

公开(公告)号：US20180061775A1

公开(公告)日：2018-03-01

申请号：US15253782

申请日：2016-08-31

Applicant: QUALCOMM Incorporated

Inventor： Mario Velez ,  Niranjan Sunil Mudakatte ,  Changhan Yun ,  David Berdy ,  Shiqun Gu ,  Jonghae Kim ,  Chengjie Zuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

公开(公告)号：US20180040547A1

公开(公告)日：2018-02-08

申请号：US15231512

申请日：2016-08-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L23/498 ,  H01L27/092 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76264 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L27/092 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/08146 ,  H01L2224/08237 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8285 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06572 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L21/76898

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.