公开(公告)号：US10298244B2

公开(公告)日：2019-05-21

申请号：US15605932

申请日：2017-05-25

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar

IPC: H03L7/06 ,  H03L7/23 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

公开(公告)号：US10230384B2

公开(公告)日：2019-03-12

申请号：US15818434

申请日：2017-11-20

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Kenneth C. Dyer ,  Nhat Nguyen ,  Shankar Tangirala

IPC: H03M1/00 ,  H04L25/03 ,  H03M1/14 ,  H03M1/36

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

公开(公告)号：US10205458B2

公开(公告)日：2019-02-12

申请号：US15644632

申请日：2017-07-07

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03L7/16 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/24 ,  H03L7/099

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

公开(公告)号：US20180278210A1

公开(公告)日：2018-09-27

申请号：US15921480

申请日：2018-03-14

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar ,  Mohammad Hekmat ,  Reza Navid

IPC: H03B19/00 ,  H03K3/03 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00 ,  H03L7/099

CPC classification number: H03B19/00 ,  G06F1/08 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03L7/099 ,  H05K999/99

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

公开(公告)号：US09692431B2

公开(公告)日：2017-06-27

申请号：US14746618

申请日：2015-06-22

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Farshid Aryanfar

IPC: H03L7/00 ,  H03L7/23 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18

CPC classification number: H03L7/235 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L7/23

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

公开(公告)号：US09397868B1

公开(公告)日：2016-07-19

申请号：US14050223

申请日：2013-10-09

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Jared L. Zerbe

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03057 ,  H03L7/00 ,  H04L7/0087 ,  H04L7/033

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Abstract translation: 本公开提供了分路通均衡器和时钟恢复电路。 更具体地，通过分别均衡数据路径和边缘路径中的每一个，特别是在高信令速率下，时钟恢复操作被增强。 在具体实施例中，以使信噪比最大化的方式均衡数据路径，并且以强调单个单位间隔的对称边缘响应并且对于其它单位间隔为零边缘响应的方式均衡边缘路径（例如， 不考虑峰值电压裕度）。 这种均衡使边缘分组变紧，从而增强时钟恢复，同时优化数据路径采样。 还公开了用于寻址分路均衡引起的偏移的技术。

公开(公告)号：US20150333760A1

公开(公告)日：2015-11-19

申请号：US14651571

申请日：2014-01-03

Applicant: RAMBUS INC.

Inventor： Jared L. Zerbe ,  Masum Hossain

IPC: H03L7/24 ,  H03L7/06 ,  H03L1/00

CPC classification number: H03L7/24 ,  H03K3/0307 ,  H03K3/0315 ,  H03L1/00 ,  H03L7/06

Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Abstract translation: 描述了包括用于确定注入锁定振荡器（ILO）的设置的电路的集成电路（IC）的实施例。 在一些实施例中，基于参考时钟信号的第一时钟沿产生注入信号，并将其注入国际劳工组织。 接下来，基于参考时钟信号的第二时钟沿对ILO的一个或多个输出信号进行采样，并且基于样本确定ILO的设置。 在一些实施例中，基于参考时钟信号和自由运行的ILO生成两个或更多个时间数字（TDC）码的序列。 在一些实施例中，已经存在于延迟锁定环路中的TDC电路被重新用于确定两个或多个TDC码的序列。 然后可以基于两个或多个TDC代码的顺序来确定ILO设置。

公开(公告)号：US20130121094A1

公开(公告)日：2013-05-16

申请号：US13676945

申请日：2012-11-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

IPC: H03L7/091 ,  G11C8/18

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

公开(公告)号：US11792057B2

公开(公告)日：2023-10-17

申请号：US17852922

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Richelle L. Smith ,  Carl W. Werner

IPC: H04L27/20 ,  H04L27/233 ,  H04L27/34

CPC classification number: H04L27/2338 ,  H04L27/2057 ,  H04L27/2337 ,  H04L27/3411

Abstract: A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first output data symbol. The receiver furthermore samples the second data signal based on signal transition timing of the first data signal to generate a second output data symbol.

公开(公告)号：US11706060B2

公开(公告)日：2023-07-18

申请号：US17460774

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Haidang Lin ,  Charles Walter Boecker ,  Masum Hossain

IPC: H03F3/45 ,  H04L25/03 ,  H04L25/49 ,  H03K5/15

CPC classification number: H04L25/03878 ,  H04L25/03267 ,  H04L25/03847 ,  H04L25/4927 ,  H03F3/45183 ,  H03K5/15013 ,  H04L2025/03535

Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.