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    Disposing underfill in an integrated circuit structure
    51.
    发明授权
    Disposing underfill in an integrated circuit structure 有权
    在集成电路结构中处理底部填充物

    公开(公告)号：US08546191B2

    公开(公告)日：2013-10-01

    申请号：US12958309

    申请日：2010-12-01

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： H01L21/60

    CPC分类号： H01L21/563 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/73203

    摘要： In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

    摘要翻译： 在一个实施例中，提供了一种形成多芯片半导体器件的方法。 多个骰子安装在半导体衬底上，并且相邻骰子之间的相邻骰子被分开一段距离，在该距离处，相邻骰子中的第一个骰子将在底部填充期间与邻近骰子的凸缘的弯液面接触，以形成毛细管桥， 相邻的骰子。 焊接凸块被回流以将多个裸片的接触端子电连接到衬底的顶表面上的接触端子。 底部填充物沉积在多个骰子中的一个或多个骰子的一个或多个边缘上。 作为在相邻骰子之间形成的毛细管桥的结果，在相邻骰子的底表面和衬底的顶表面之间引起底部填充物的流动。 分配的底部填充物固化。

    Customizing metal pattern density in die-stacking applications
    52.
    发明授权
    Customizing metal pattern density in die-stacking applications 有权
    定制模具堆叠应用中的金属图案密度

    公开(公告)号：US08296689B1

    公开(公告)日：2012-10-23

    申请号：US12419234

    申请日：2009-04-06

    申请人： Arifur Rahman ,  Hong-tsz Pan

    发明人： Arifur Rahman ,  Hong-tsz Pan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.

    摘要翻译： 描述了用于设计集成电路（IC）的方法，装置和计算机可读介质。 在一些示例中，获得了描述集成电路的导电层的布局数据。 分析布局数据，以便通过（TDV）区域识别。 为集成电路的设计规则中具有最大金属密度的每个TDV区域创建金属填充图案。 每个TDV区域的金属填充图案与布局数据合并。

    Unified design methodology for multi-die integrated circuits
    54.
    发明授权
    Unified design methodology for multi-die integrated circuits 有权
    多模集成电路的统一设计方法

    公开(公告)号：US08156456B1

    公开(公告)日：2012-04-10

    申请号：US12829213

    申请日：2010-07-01

    申请人： Arifur Rahman ,  Min-Hsing Chen

    发明人： Arifur Rahman ,  Min-Hsing Chen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/74

    摘要： A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. The first PNS library can be correlated with a first die of the IC. The second PNS library can be correlated with the second die of the IC. Via a processor, a circuit element can be defined within a circuit design implemented within the IC according to the PNS library correlated to the die in which the circuit element is located.

    摘要翻译： 设计具有多个管芯的集成电路（IC）的方法可以包括识别具有用于第一IC工艺技术的第一工艺节点特定（PNS）库和用于第二IC工艺技术的第二PNS库的统一设计库。 第一个PNS库可以与IC的第一个管芯相关联。 第二个PNS库可以与IC的第二个管芯相关联。 通过处理器，可以根据与电路元件所在的管芯相关联的PNS库，在IC内实现的电路设计中定义电路元件。

    Integrated circuit with through-die via interface for die stacking and cross-track routing
    55.
    发明授权
    Integrated circuit with through-die via interface for die stacking and cross-track routing 有权
    集成电路，具有通孔接口，用于芯片堆叠和交叉轨道路由

    公开(公告)号：US08089299B1

    公开(公告)日：2012-01-03

    申请号：US12436918

    申请日：2009-05-07

    申请人： Arifur Rahman ,  Bernard J. New

    发明人： Arifur Rahman ,  Bernard J. New

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17796

    摘要： An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

    摘要翻译： 描述了一种集成电路管芯，其包括以列排列的瓦片阵列。 集成电路管芯包括具有至少一排通孔的界面砖。 集成电路管芯包括包括水平布线轨道和包括垂直布线轨道的金属层的金属层。 具有垂直布线段的至少一些金属层包括水平布线段。 每个水平布线段耦合到水平布线轨道的第一布线段，该第一布线段由至少一行贯通管道通孔中断，并且连接到由至少一个中断的水平布线轨道的第二布线段 一排穿过通孔。 每个水平布线段在至少一排通孔通孔之间延伸，并且在邻接的界面砖中延伸至少一排通孔。

    Software model for a hybrid stacked field programmable gate array
    58.
    发明授权
    Software model for a hybrid stacked field programmable gate array 有权
    混合堆叠现场可编程门阵列的软件模型

    公开(公告)号：US07930661B1

    公开(公告)日：2011-04-19

    申请号：US12185511

    申请日：2008-08-04

    申请人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

    发明人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.

    摘要翻译： 层叠集成电路系统（600）的软件模型（620）包括通过芯片间通信接口（606）连接到第二集成电路管芯（604）的第一集成电路管芯（602）。 第一集成电路管芯的软件模型包括集成电路资源（614）和内部接口（150）。 第二集成电路管芯的软件模型包括堆叠资源（618）。 内部接口的软件模型可配置为通过芯片间通信接口将第二个集成电路管芯的堆叠资源连接到集成电路资源。

    Hardware stack structure using programmable logic
    59.
    发明授权
    Hardware stack structure using programmable logic 有权
    硬件堆栈结构采用可编程逻辑

    公开(公告)号：US07500060B1

    公开(公告)日：2009-03-03

    申请号：US11724808

    申请日：2007-03-16

    申请人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

    发明人： James B. Anderson ,  Sean W. Kao ,  Arifur Rahman

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0875 ,  G06F7/785

    摘要： A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.

    摘要翻译： 使用可编程逻辑的硬件堆栈（HSTACK）结构可以包括查找表（LUT）随机存取存储器（RAM）电路和LUT RAM电路内的电路，用于向上和向下传播数据。 硬件结构可以通过向顶部，底部或顶部和底部之间的部分添加堆叠而任意组装成更大的结构。 硬件堆栈结构还可以包括耦合到现场可编程门阵列（FPGA）结构内的HSTACK结构的虚拟堆栈（VSTACK）结构。 VSTACK可以以附加的外围存储器和高速缓存控制的形式排列，以便虚拟扩展到HSTACK地址空间。 硬件堆叠结构还可以包括辅助复位电路。

    Circuit for and method of enabling partial reconfiguration of a device having programmable logic
    60.
    发明授权
    Circuit for and method of enabling partial reconfiguration of a device having programmable logic 有权
    具有可编程逻辑的器件的部分重新配置的电路和方法

    公开(公告)号：US07477072B1

    公开(公告)日：2009-01-13

    申请号：US11333972

    申请日：2006-01-17

    申请人： Sean Kao ,  Arifur Rahman ,  James Anderson

    发明人： Sean Kao ,  Arifur Rahman ,  James Anderson

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a configurable logic block; and a reset signal coupled to the block of memory elements, the reset signal enabling partial reconfiguration of the memory cells of the configurable logic block. Each the memory cell may be coupled to receive the reset signal enabling the partial reconfiguration of the block of memory cells of the configurable logic block. The reset signal may comprise a plurality of signals, wherein each signal of the plurality of signals is coupled to a memory cell of the block of memory cells. Each memory cell may also receive a signal for setting an initial state. A method of enabling partial reconfiguration of memory cells of a look-up table of a programmable logic device is also described.

    摘要翻译： 描述了一种用于实现具有可编程逻辑的设备的存储器元件的部分重新配置的电路。 该电路包括一组存储器单元，其包括可配置逻辑块的查找表; 以及耦合到所述存储器单元块的复位信号，所述复位信号使得能够对所述可配置逻辑块的存储器单元进行部分重新配置。 每个存储器单元可以被耦合以接收复位信号，从而能够对可配置逻辑块的存储器单元块进行部分重新配置。 复位信号可以包括多个信号，其中多个信号中的每个信号耦合到存储器单元块的存储单元。 每个存储单元也可以接收用于设置初始状态的信号。 还描述了启用可编程逻辑器件的查找表的存储器单元的部分重新配置的方法。