公开(公告)号：US11849584B2

公开(公告)日：2023-12-19

申请号：US17422883

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato

IPC: G11C16/10 ,  H10B43/27 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02 ,  H01L29/24 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02565 ,  H01L29/24 ,  H10B43/40

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.

公开(公告)号：US11711922B2

公开(公告)日：2023-07-25

申请号：US16925648

申请日：2020-07-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Shunpei Yamazaki

IPC: G11C16/10 ,  H10B43/40 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out.

公开(公告)号：US11670344B2

公开(公告)日：2023-06-06

申请号：US17540314

申请日：2021-12-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki Atsumi ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

CPC classification number: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/1225 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US10304523B2

公开(公告)日：2019-05-28

申请号：US14705698

申请日：2015-05-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

公开(公告)号：US10050060B2

公开(公告)日：2018-08-14

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Yuichi Sato ,  Yuji Asano ,  Tetsunori Maruyama ,  Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/78 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8258

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US10037798B2

公开(公告)日：2018-07-31

申请号：US15603570

申请日：2017-05-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C5/06 ,  G11C11/56 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4076

CPC classification number: G11C11/565 ,  G11C11/403 ,  G11C11/4076 ,  G11C11/4091

Abstract: To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.

公开(公告)号：US09852787B2

公开(公告)日：2017-12-26

申请号：US15464395

申请日：2017-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C11/419 ,  G11C5/14 ,  G06F3/06 ,  G11C14/00

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

公开(公告)号：US09715906B2

公开(公告)日：2017-07-25

申请号：US14502209

申请日：2014-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Tatsuya Onuki

IPC: G11C5/14 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/12 ,  H01L29/78

CPC classification number: G11C5/145 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78696

Abstract: A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.

公开(公告)号：US09673224B2

公开(公告)日：2017-06-06

申请号：US14515993

申请日：2014-10-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidekazu Miyairi

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

公开(公告)号：US09502094B2

公开(公告)日：2016-11-22

申请号：US13892479

申请日：2013-05-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C11/40 ,  G11C14/00 ,  H01L27/11 ,  H01L27/12

CPC classification number: G11C11/40 ,  G11C14/0063 ,  H01L27/1108 ,  H01L27/1225

Abstract: To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.

Abstract translation: 提供即使不提供电源也保持存储的逻辑状态的存储元件。 通过在短时间内有助于停止对存储元件供电的功率来增加降低功耗的效果。 保持在逻辑电路中的节点中的数据（电位）可以迅速地保存在晶体管的源极和漏极之一以及包含在存储器电路中的电容器的一个电极中的一个通过降低另一个的电位而连接的节点 在晶体管导通之前的电容器的电极。 当晶体管处于断开状态时，当晶体管处于导通状态时，通过使电容器的另一个电极的电位高于电容器的另一个电极的电位，即使没有 供电。