公开(公告)号：US08866305B2

公开(公告)日：2014-10-21

申请号：US13937779

申请日：2013-07-09

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L21/20 ,  H01L25/00 ,  H01L27/06 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2221/6839 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/05009 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80065 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00

Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.

Abstract translation: 形成键合的半导体结构的方法包括暂时将半导体结构直接结合在一起，使半导体结构中的至少一个变薄，然后将稀化的半导体结构永久地结合到另一个半导体结构。 可以在不使用粘合剂的情况下建立临时的直接粘合。 结合的半导体结构根据这样的方法制造。

公开(公告)号：US20250004196A1

公开(公告)日：2025-01-02

申请号：US18702411

申请日：2022-10-21

Applicant: Soitec

Inventor： Ionut Radu ,  Christophe Maleville

IPC: G02B6/12 ,  G02B6/13

Abstract: A photonic-electronic integrated-circuit chip is formed on a semiconductor-on-insulator substrate. The silicon-on-insulator substrate has an embedded dielectric layer and an active layer of semiconductor material. The chip includes an electronic circuit portion and a photonic interconnection interface of the electronic circuit portion which are co-integrated in the active layer. The electronic circuit portion is formed in an active layer region, the thickness of which is greater than the thickness of an active layer region in which the photonic interface is formed.

公开(公告)号：US20240396520A1

公开(公告)日：2024-11-28

申请号：US18790454

申请日：2024-07-31

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/64 ,  H10N30/072 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086 ,  H10N30/853 ,  H10N35/01

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20240030033A1

公开(公告)日：2024-01-25

申请号：US18257217

申请日：2021-11-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  SOITEC

Inventor： Gweltaz Gaudin ,  Ionut Radu ,  Franck Fournel ,  Julie Widiez ,  Didier Landru

IPC: H01L21/18 ,  H01L21/762 ,  H01L21/02 ,  H01L21/322

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/02002 ,  H01L21/3221

Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

公开(公告)号：US20230253949A1

公开(公告)日：2023-08-10

申请号：US18302878

申请日：2023-04-19

Applicant: Soitec

Inventor： Pascal Guenard ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10 ,  H10N30/02 ,  H10N30/086 ,  H10N30/87 ,  H10N30/88 ,  H03H9/145

CPC classification number: H03H9/02834 ,  H03H3/10 ,  H03H9/02574 ,  H10N30/02 ,  H10N30/086 ,  H10N30/875 ,  H10N30/883 ,  H03H9/02984 ,  H03H9/145 ,  H03H9/64

Abstract: A production method for a surface acoustic wave device comprises the following steps: a step of providing a piezoelectric substrate comprising a transducer arranged on the main front face; a step of depositing a dielectric encapsulation layer on the main front face of the piezoelectric substrate and on the transducer; and a step of assembling the dielectric encapsulation layer with the main front face of a support substrate having a coefficient of thermal expansion less than that of the piezoelectric substrate. In additional embodiments, a surface acoustic wave device comprises a layer of piezoelectric material equipped with a transducer on a main front face, arranged on a substrate support of which the coefficient of thermal expansion is less than that of the piezoelectric material. The transducer is arranged in a dielectric encapsulation layer, between the layer of piezoelectric material and the support substrate.

公开(公告)号：US20230217832A1

公开(公告)日：2023-07-06

申请号：US18179071

申请日：2023-03-06

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Ionut Radu ,  Jean-Marc Bethoux

IPC: H10N30/853 ,  C30B25/18 ,  C30B29/22 ,  H10N30/20 ,  H10N30/072 ,  H10N30/079 ,  H10N30/085 ,  H10N30/00 ,  H03H3/02 ,  H03H3/08 ,  H03H9/25 ,  H03H9/54 ,  H03H9/64

CPC classification number: H10N30/8542 ,  C30B25/186 ,  C30B29/22 ,  H10N30/20 ,  H10N30/072 ,  H10N30/079 ,  H10N30/085 ,  H10N30/10516 ,  H03H3/02 ,  H03H3/08 ,  H03H9/25 ,  H03H9/54 ,  H03H9/64 ,  C30B29/30

Abstract: A composite substrate includes a final substrate, and a piezoelectric material directly molecularly bonded to the final substrate at a first interface. The piezoelectric material comprises an epitaxial layer, but does not comprise a seed layer. Additional composite substrates include a final substrate, and a piezoelectric material directly molecularly bonded to the final substrate at a first interface. The piezoelectric material comprises an epitaxial layer. The composite substrate further includes a seed layer on which the piezoelectric material has been epitaxially grown. The seed layer is disposed on a side of the epitaxial layer opposite the final substrate. An acoustic wave device comprises such a composite substrate with at least one electrode on a surface of the piezoelectric layer opposite the substrate.

公开(公告)号：US11637542B2

公开(公告)日：2023-04-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/08 ,  H03H3/04 ,  H03H9/64 ,  H01L41/312 ,  H01L41/313 ,  H01L41/187 ,  H03H3/10 ,  H01L41/47 ,  H01L41/332 ,  H01L41/337

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US11367650B2

公开(公告)日：2022-06-21

申请号：US17109978

申请日：2020-12-02

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US20210143053A1

公开(公告)日：2021-05-13

申请号：US17109978

申请日：2020-12-02

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US10943815B2

公开(公告)日：2021-03-09

申请号：US16308602

申请日：2017-06-06

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.