公开(公告)号：US5563428A

公开(公告)日：1996-10-08

申请号：US380782

申请日：1995-01-30

申请人： Bruce A. Ek ,  Stephen M. Gates ,  Fernando J. Guarin ,  Subramanian S. Iyer ,  Adrian R. Powell

发明人： Bruce A. Ek ,  Stephen M. Gates ,  Fernando J. Guarin ,  Subramanian S. Iyer ,  Adrian R. Powell

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L21/20 ,  H01L27/12 ,  H01L31/10 ,  H01L31/18 ,  H01L33/00 ,  H01S5/00 ,  H01S5/323 ,  H01L31/0312 ,  H01L27/108 ,  H01L31/0328

CPC分类号： H01L33/007 ,  H01L21/0445 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A structure is fabricated comprising a substrate, a dielectric layer formed over the substrate, and a single crystal layer of a compound formed over the dielectric layer. The single crystal layer is formed by the chemical reaction of at least a first element with an initial single crystal layer of a second element on the dielectric layer having an initial thickness of about 100 to about 10,000 angstroms.According to another aspect, a carbide single crystal layer is provided on a substrate by depositing carbon from a solid carbon source at a low rate and low temperature, followed by reacting the carbon with the underlying layer to convert it to the carbide.

摘要翻译： 制造的结构包括衬底，在衬底上形成的电介质层和在电介质层上形成的化合物的单晶层。 单晶层通过至少第一元素与电介质层上初始厚度为约100至约10,000埃的第二元素的初始单晶层的化学反应形成。 根据另一方面，通过在低速率和低温下从固体碳源沉积碳，然后使碳与下层反应以将其转化为碳化物，在基板上提供碳化物单晶层。

公开(公告)号：US08637957B1

公开(公告)日：2014-01-28

申请号：US13552293

申请日：2012-07-18

申请人： Chih-Chao Yang ,  Stephen M. Gates

发明人： Chih-Chao Yang ,  Stephen M. Gates

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/165 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53247 ,  H01L23/5329 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

摘要翻译： 提供一种抗熔丝结构，其中抗熔丝材料衬垫嵌入设置在互连电介质材料内的一个开口内。 反熔丝材料衬垫位于第一导电金属和第二导电金属之间，第一导电金属和第二导电金属也存在于开口内。 扩散阻挡衬里将第一导电金属与互连电介质材料的任何部分分开。 反熔丝结构横向邻近形成在与反熔丝结构相同的互连电介质材料内的互连结构。

公开(公告)号：US20130049207A1

公开(公告)日：2013-02-28

申请号：US13221698

申请日：2011-08-30

申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

IPC分类号： H01L21/26 ,  H01L23/485 ,  H01L21/66

CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

公开(公告)号：US20110271141A1

公开(公告)日：2011-11-03

申请号：US12771293

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G06F11/008 ,  G06F11/0724 ,  G06F11/0787 ,  G06F11/0793

摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.

摘要翻译： 提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。 耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。 片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。 片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。 即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。 片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

公开(公告)号：US07948083B2

公开(公告)日：2011-05-24

申请号：US11763135

申请日：2007-06-14

申请人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

发明人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

IPC分类号： H01L29/40

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法至少包括化学机械抛光和UV曝光或化学修复处理的步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US07517790B2

公开(公告)日：2009-04-14

申请号：US10906189

申请日：2005-02-08

申请人： John A. Fitzsimmons ,  Stephen M. Gates ,  Michael W. Lane ,  Eric G. Liniger

发明人： John A. Fitzsimmons ,  Stephen M. Gates ,  Michael W. Lane ,  Eric G. Liniger

IPC分类号： H01L21/44

CPC分类号： H01L23/564 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

摘要翻译： 公开了一种修复诸如高速半导体微处理器，专用集成电路（ASIC）和其它高速集成电路器件的半导体芯片上的引线键合损伤的方法，特别是使用低K电介质材料的器件。 该方法涉及使用反应性液体的表面改性。 在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗 湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

公开(公告)号：US20070296064A1

公开(公告)日：2007-12-27

申请号：US11472726

申请日：2006-06-22

申请人： Stephen M. Gates ,  Robert D. Miller

发明人： Stephen M. Gates ,  Robert D. Miller

IPC分类号： H01L23/52 ,  H01L21/469 ,  C01B35/00 ,  C01B25/00

CPC分类号： H01L21/02112 ,  H01L21/02205 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.

摘要翻译： 提供了一种致密的硼基或磷基介电材料。 具体地说，本发明提供由硼和碳，氮和氢中的至少一种构成的致密的硼基介电材料或由磷和氮组成的致密的磷基电介质。 本发明还提供了电子结构，其包含致密的硼基或磷基电介质作为蚀刻停止层，电介质铜封盖材料，CMP停止层和/或ULSI后端的反应离子蚀刻掩模 （BEOL）互连结构。 在本发明中还描述了形成本发明的硼基或磷基电介质的方法以及含有它们的电子结构。

公开(公告)号：US07088003B2

公开(公告)日：2006-08-08

申请号：US10780554

申请日：2004-02-19

申请人： Stephen M. Gates ,  Son Nguyen

发明人： Stephen M. Gates ,  Son Nguyen

IPC分类号： H05K3/20 ,  H05K1/11

CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

摘要： An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the ULK dielectric. Disclosed are also methods of fabrication of BEOL interconnect structures, including (i) methods in which a dense TDL is provided on etched opening of a ULK dielectric and (ii) methods in which a ULK dielectric is placed in a process chamber on a cold chuck, a sealing agent is added to the process chamber, and an activation step is performed.

摘要翻译： 提供包括超低k（ULK）电介质的线（BEOL）互连结构的改进的后端。 该结构可以是单镶嵌型或双镶嵌型，并且在金属阻挡层和ULK电介质之间包括致密的薄介电层（TDL）。 公开了制造BEOL互连结构的方法，包括（i）其中在ULK电介质的蚀刻开口上提供致密TDL的方法，以及（ii）将ULK电介质放置在冷卡盘上的处理室中的方法 ，在处理室中加入密封剂，进行活化工序。

公开(公告)号：US06989575B2

公开(公告)日：2006-01-24

申请号：US10080568

申请日：2002-02-25

申请人： Stephen M. Gates ,  Roy E. Scheuerlein

发明人： Stephen M. Gates ,  Roy E. Scheuerlein

IPC分类号： H01L29/82 ,  H01L43/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L21/76254 ,  H01L27/224

摘要： Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

公开(公告)号：US06939797B2

公开(公告)日：2005-09-06

申请号：US10706773

申请日：2003-11-12

申请人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

发明人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

IPC分类号： H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/461

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括具有低介电常数（低-k）的扩散阻挡层或覆盖层，其中通过等离子体增强化学气相沉积（PE CVD）工艺，覆盖层由氮化硅形成。 金属化结构还包括由具有小于约4的介电常数的含碳电介质材料形成的层间电介质（ILD），以及优选由氮化硅或碳化硅形成的ILD上的连续硬掩模层。 还公开了一种用于形成BEOL金属化结构的方法。 该方法包括预清洁或预激活步骤，以改善盖层与下面的铜导体的粘合性。 预清洁或预活化步骤包括将铜表面暴露于包括氢，氨，氮和/或惰性气体的还原等离子体。