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    Formation of arrays of microelectronic elements
    1.
    发明授权
    Formation of arrays of microelectronic elements 失效
    形成微电子元件阵列

    公开(公告)号：US06391658B1

    公开(公告)日：2002-05-21

    申请号：US09427251

    申请日：1999-10-26

    申请人： Stephen M. Gates ,  Roy E. Scheuerlein

    发明人： Stephen M. Gates ,  Roy E. Scheuerlein

    IPC分类号： H01L2100

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L21/76254 ,  H01L27/224

    摘要： Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

    摘要翻译： 通过涉及主晶片和第一晶片的方法，通过包括双栅极FET的微电子元件阵列，诸如磁性捕获存储元件和FET的阵列来制造其上分开形成微电子元件的一部分的第一晶片。 诸如金属填充的通孔的导电元件形成在主晶片中并延伸到其表面。 在第一晶片中的选定深度处注入氢离子。 在第一晶片的氢离子注入深度之上形成微电子元件的选定部分之后，将其结合到主晶片的表面，使得两个晶片的互补部分可以结合以形成微电子元件。 第一晶片在氢离子注入深度处断裂，并且其下部被去除以允许在其上抛光和固定电极。

    Formation of arrays of microelectronic elements
    2.
    发明授权
    Formation of arrays of microelectronic elements 失效

    公开(公告)号：US06989575B2

    公开(公告)日：2006-01-24

    申请号：US10080568

    申请日：2002-02-25

    申请人： Stephen M. Gates ,  Roy E. Scheuerlein

    发明人： Stephen M. Gates ,  Roy E. Scheuerlein

    IPC分类号： H01L29/82 ,  H01L43/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L21/76254 ,  H01L27/224

    摘要： Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.

    BEOL structures incorporating active devices and mechanical strength
    3.
    发明授权
    BEOL structures incorporating active devices and mechanical strength 有权
    包含有源器件和机械强度的BEOL结构

    公开(公告)号：US08624323B2

    公开(公告)日：2014-01-07

    申请号：US13149797

    申请日：2011-05-31

    申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

    摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

    摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

    ELECTRICAL FUSE AND METHOD OF MAKING THE SAME
    5.
    发明申请
    ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 有权
    电保险丝及其制造方法

    公开(公告)号：US20120261793A1

    公开(公告)日：2012-10-18

    申请号：US13085568

    申请日：2011-04-13

    申请人： Chih-Chao Yang ,  Stephen M. Gates ,  Baozhen Li ,  Daniel C. Edelstein

    发明人： Chih-Chao Yang ,  Stephen M. Gates ,  Baozhen Li ,  Daniel C. Edelstein

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.

    摘要翻译： 一种改进的电熔丝（e-fuse）装置，包括具有第一顶表面的电介质层，嵌入介质层中的两个导电特征和熔丝元件。 每个导电特征具有第二顶表面和直接在第二顶表面上的金属帽。 每个金属盖具有在介电层的第一顶表面之上的第三顶表面。 熔丝元件位于每个金属盖的第三顶表面上，并位于介质层的第一顶表面上。 还提供了形成电熔丝装置的方法。

    Pseudo hybrid structure for low K interconnect integration
    6.
    发明授权
    Pseudo hybrid structure for low K interconnect integration 有权
    用于低K互连集成的伪混合结构

    公开(公告)号：US07955968B2

    公开(公告)日：2011-06-07

    申请号：US12399372

    申请日：2009-03-06

    申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

    发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

    摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

    摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。

    SiCOH film preparation using precursors with built-in porogen functionality
    8.
    发明授权
    SiCOH film preparation using precursors with built-in porogen functionality 有权
    使用具有内置致孔剂功能的前体的SiCOH膜制备

    公开(公告)号：US07521377B2

    公开(公告)日：2009-04-21

    申请号：US11329560

    申请日：2006-01-11

    申请人： Stephen M. Gates ,  Alfred Grill ,  Robert D. Miller ,  Deborah A. Neumayer ,  Son Nguyen

    发明人： Stephen M. Gates ,  Alfred Grill ,  Robert D. Miller ,  Deborah A. Neumayer ,  Son Nguyen

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31695 ,  B05D1/60 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351

    摘要： A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving group. The use of an organosilicon precursor containing a molecular scale sacrificial leaving group enables control of the pore size at the nanometer scale, control of the compositional and structural uniformity and simplifies the manufacturing process. Moreover, fabrication of a dielectric film from a single precursor enables better control of the final porosity in the film and a narrower pore size distribution resulting in better mechanical properties at the same value of dielectric constant.

    摘要翻译： 描述了使用至少一种有机硅前体制造具有超低介电常数（或超低k）的介电材料的方法。 本发明中使用的有机硅前体包括含有Si-O结构和牺牲有机基团的分子作为离去基团。 使用含有分子尺度牺牲离去基团的有机硅前体使得能够控制纳米尺度的孔径，控制组成和结构均匀性并简化制造过程。 此外，从单一前体制造电介质膜能够更好地控制膜中的最终孔隙率和较窄的孔径分布，导致在相同的介电常数值下更好的机械性能。