公开(公告)号：US10103223B2

公开(公告)日：2018-10-16

申请号：US15182859

申请日：2016-06-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L27/06 ,  H01L27/08 ,  H01L29/8605 ,  H01L29/868 ,  H01L49/02 ,  H01L21/265 ,  H01L21/74 ,  H01L21/762 ,  H01L23/528 ,  H01L29/45

摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

公开(公告)号：US10020361B2

公开(公告)日：2018-07-10

申请号：US15201130

申请日：2016-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/205 ,  H01L21/306

CPC分类号： H01L29/0661 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

摘要： A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

公开(公告)号：US09985103B2

公开(公告)日：2018-05-29

申请号：US15362465

申请日：2016-11-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Wei Yao ,  Chen-Ju Yu ,  King-Yuen Wong ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chun-Lin Tsai

IPC分类号： H01L29/66 ,  H01L29/45 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L29/417 ,  H01L29/778 ,  H01L29/08

CPC分类号： H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

公开(公告)号：US20170338316A1

公开(公告)日：2017-11-23

申请号：US15670135

申请日：2017-08-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Wei Yao ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung ,  King-Yuen Wong

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

公开(公告)号：US09680009B2

公开(公告)日：2017-06-13

申请号：US14926582

申请日：2015-10-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Karthick Murukesan ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Chih-Yuan Chan ,  Yi-Min Chen ,  Chen-Chien Chang ,  Chiu-Hua Chung ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/7816 ,  H01L23/5225 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402

摘要： In some embodiments, a semiconductor device includes a transistor, an isolation component, and a conductive layer. The transistor includes a source region and a drain region. The isolation component surrounds the source region. The conductive layer is configured for interconnection of the drain region. The conductive component is between the conductive layer and the isolation component, configured to shield the isolation component from an electric field over the isolation component.

公开(公告)号：US09502311B2

公开(公告)日：2016-11-22

申请号：US14872197

申请日：2015-10-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC分类号： H01L29/778 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L27/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L29/20

CPC分类号： H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

摘要： A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

摘要翻译： 提供了其上设置III-V化合物层的硅衬底。 通过离子注入工艺在硅衬底中形成二极管。 二极管形成在硅衬底和III-V化合物层之间的界面附近。 通过III-V化合物层蚀刻开口以暴露二极管。 开口填充有导电材料。 由此，形成与二极管耦合的通孔。 至少部分地在III-V化合物层中形成高电子迁移率晶体管（HEMT）器件。

公开(公告)号：US09412835B2

公开(公告)日：2016-08-09

申请号：US14790588

申请日：2015-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC分类号： H01L21/82 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20

CPC分类号： H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

摘要： An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

公开(公告)号：US09391195B2

公开(公告)日：2016-07-12

申请号：US14074802

申请日：2013-11-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L29/861 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L29/7816 ,  H01L21/76202 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/861

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中并具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

公开(公告)号：US09379188B2

公开(公告)日：2016-06-28

申请号：US14967676

申请日：2015-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ker-Hsiao Huo ,  Chih-Chang Cheng ,  Fu-Chih Yang ,  Jen-Hao Yeh ,  Chun Lin Tsai ,  Ru-Yi Su

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7394 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

摘要翻译： 公开了制造高压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）的方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

公开(公告)号：US20160141418A1

公开(公告)日：2016-05-19

申请号：US15004438

申请日：2016-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun-Lin Tsai

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/808

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.