Priority Based Backup in Nonvolatile Logic Arrays
    51.
    发明申请
    Priority Based Backup in Nonvolatile Logic Arrays 有权
    非易失逻辑阵列中基于优先级的备份

    公开(公告)号:US20140075087A1

    公开(公告)日:2014-03-13

    申请号:US13770004

    申请日:2013-02-19

    Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.

    Abstract translation: 处理设备基于优先级或合并结构有选择地仅备份某些数据。 在一种方法中,非易失性逻辑控制器通过将表示机器状态的数据的一部分存储在非易失性逻辑元件阵列中而不是机器状态的所有数据来存储机器状态。 因此,非易失性逻辑控制器通过根据用于备份和恢复的第一类别存储机器状态的第一组程序数据来存储多个非易失性逻辑单元阵列中的机器状态,并存储第二组程序 根据用于备份和恢复的第二类别的机器状态的数据。

    Clock oscillator control circuit
    54.
    发明授权

    公开(公告)号:US11860686B2

    公开(公告)日:2024-01-02

    申请号:US17960383

    申请日:2022-10-05

    CPC classification number: G06F1/08 G06F1/12 H03K5/00006 H03K2005/00058

    Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

    Dual-port negative level sensitive preset data retention latch
    59.
    发明授权
    Dual-port negative level sensitive preset data retention latch 有权
    双端口负电平敏感预设数据保持锁存器

    公开(公告)号:US09520863B2

    公开(公告)日:2016-12-13

    申请号:US14447911

    申请日:2014-07-31

    CPC classification number: H03K3/356008

    Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

    Abstract translation: 在本发明的一个实施例中,双端口负电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低,CLKZ变为高电平,预置控制信号PRE为低电平,保持控制信号RET为低电平时,数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出,第二数据位D2,时钟信号CKT和CLKZ,保持控制信号RET和RETN,预置控制信号PRE和控制信号SS和SSN。 信号CKT,CLKZ,RET,RETN,PRE,SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间,控制信号RET和RETN确定数据是否存储在双端口锁存器中。

    Non-volatile logic based processing device
    60.
    发明授权
    Non-volatile logic based processing device 有权
    基于非易失性逻辑的处理器件

    公开(公告)号:US09454437B2

    公开(公告)日:2016-09-27

    申请号:US14309362

    申请日:2014-06-19

    CPC classification number: G06F11/1417 G06F9/4401 G06F9/4418 G06F11/1469

    Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

    Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件(NVL)阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效,则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导,则执行标准引导序列以确定数据的第二部分,然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分,该部分未从其他非易失性设备读取数据,以避免相应的电源域超载。

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