公开(公告)号：US20140075087A1

公开(公告)日：2014-03-13

申请号：US13770004

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.

Abstract translation: 处理设备基于优先级或合并结构有选择地仅备份某些数据。 在一种方法中，非易失性逻辑控制器通过将表示机器状态的数据的一部分存储在非易失性逻辑元件阵列中而不是机器状态的所有数据来存储机器状态。 因此，非易失性逻辑控制器通过根据用于备份和恢复的第一类别存储机器状态的第一组程序数据来存储多个非易失性逻辑单元阵列中的机器状态，并存储第二组程序 根据用于备份和恢复的第二类别的机器状态的数据。

公开(公告)号：US12087395B2

公开(公告)日：2024-09-10

申请号：US17558847

申请日：2021-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/00 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F3/06 ,  G06F9/4401 ,  G06F11/10 ,  G06F11/14 ,  G06F12/02 ,  G06F13/00 ,  G11C7/22 ,  G11C14/00 ,  H03K3/3562

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/00 ,  Y02D30/50

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

公开(公告)号：US11953969B2

公开(公告)日：2024-04-09

申请号：US17404125

申请日：2021-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/06 ,  G06F11/07

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0688 ,  G06F11/07 ,  Y02D10/00 ,  Y02D30/50

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US11860686B2

公开(公告)日：2024-01-02

申请号：US17960383

申请日：2022-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant Lele ,  Dirk Preikszat ,  Sudhanshu Khanna ,  John Joseph Seibold

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/00006 ,  H03K2005/00058

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

公开(公告)号：US11847430B2

公开(公告)日：2023-12-19

申请号：US17521019

申请日：2021-11-08

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Hao Meng ,  Michael Zwerg ,  Christy Leigh She ,  Steven Craig Bartling

IPC: H03K5/00 ,  G06F7/62 ,  G06F1/30 ,  G06F1/26 ,  G08C13/02 ,  H03K5/24 ,  H03K21/40 ,  G11C11/56

CPC classification number: G06F7/62 ,  G06F1/26 ,  G06F1/30 ,  G08C13/02 ,  H03K5/24 ,  G11C11/56 ,  H03K21/40 ,  H03K21/403

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

公开(公告)号：US20220057996A1

公开(公告)日：2022-02-24

申请号：US17521019

申请日：2021-11-08

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Hao Meng ,  Michael Zwerg ,  Christy Leigh She ,  Steven Craig Bartling

IPC: G06F7/62 ,  G06F1/30 ,  G06F1/26 ,  G08C13/02 ,  H03K5/24

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

公开(公告)号：US11243903B2

公开(公告)日：2022-02-08

申请号：US16658928

申请日：2019-10-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F13/42 ,  G06F13/28 ,  H04L29/08

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US20170109054A1

公开(公告)日：2017-04-20

申请号：US14887885

申请日：2015-10-20

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/42 ,  H04L29/08

CPC classification number: G06F13/4234 ,  G06F13/28 ,  H04L67/303

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

公开(公告)号：US09520863B2

公开(公告)日：2016-12-13

申请号：US14447911

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/356

CPC classification number: H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US09454437B2

公开(公告)日：2016-09-27

申请号：US14309362

申请日：2014-06-19

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/44

CPC classification number: G06F11/1417 ,  G06F9/4401 ,  G06F9/4418 ,  G06F11/1469

Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。