公开(公告)号：US11855219B2

公开(公告)日：2023-12-26

申请号：US17509220

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chi-Yuan Shih ,  Chi-Wen Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L23/29 ,  H01L23/31 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

公开(公告)号：US11823964B2

公开(公告)日：2023-11-21

申请号：US17233263

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: H01L21/66 ,  C23C14/34 ,  C23C14/54 ,  G01N23/223 ,  H01J37/34 ,  H01L21/285 ,  H01L21/67

CPC classification number: H01L22/26 ,  C23C14/34 ,  C23C14/547 ,  G01N23/223 ,  H01J37/347 ,  H01L21/2855 ,  H01L21/67253 ,  G01N2223/076 ,  G01N2223/61 ,  G01N2223/633 ,  H01J2237/24585 ,  H01J2237/332

Abstract: A deposition system is provided capable of measuring at least one of the film characteristics (e.g., thickness, resistance, and composition) in the deposition system. The deposition system in accordance with the present disclosure includes a substrate process chamber. The deposition system in accordance with the present disclosure includes a substrate pedestal in the substrate process chamber, the substrate pedestal configured to support a substrate, and a target enclosing the substrate process chamber. A shutter disk including an in-situ measuring device is provided.

公开(公告)号：US11823878B2

公开(公告)日：2023-11-21

申请号：US17461742

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsi Wang ,  Yen-Yu Chen

IPC: C23C14/34 ,  H01J37/34 ,  H01L21/033

CPC classification number: H01J37/3417 ,  C23C14/3407 ,  C23C14/3414 ,  H01J37/3423 ,  H01L21/0337

Abstract: A deposition apparatus includes a process chamber, a wafer support in the process chamber, a backplane structure having a first surface in the process chamber facing the wafer support, a target having a second surface facing the first surface and a third surface facing the wafer support, and an adhesion structure in physical contact with the backplane structure and the target. The adhesion structure has an adhesion material layer, and a spacer embedded in the adhesion material layer.

公开(公告)号：US11688615B2

公开(公告)日：2023-06-27

申请号：US16997686

申请日：2020-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Hsuan-Chih Chu ,  Yen-Yu Chen

IPC: H01L21/67 ,  H01L21/324 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L21/67248 ,  H01L21/324 ,  H01L21/67103 ,  H01L22/26 ,  H01L21/67011

Abstract: A semiconductor process system includes a wafer support and a control system. The wafer support includes a plurality of heating elements and a plurality of temperature sensors. The heating elements heat a semiconductor wafer supported by the support system. The temperature sensors generate sensor signals indicative of a temperature. The control system selectively controls the heating elements responsive to the sensor signals.

公开(公告)号：US11688591B2

公开(公告)日：2023-06-27

申请号：US17876489

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsi Wang ,  Kun-Che Ho ,  Yen-Yu Chen

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/35 ,  H01L21/02

CPC classification number: H01J37/3455 ,  C23C14/3407 ,  C23C14/3442 ,  C23C14/351 ,  H01J37/3405 ,  H01J37/3414 ,  H01J37/3435 ,  H01J37/3452 ,  H01J37/3461 ,  H01L21/02631

Abstract: A an apparatus includes a processing chamber configured to house a workpiece, a target holder in the processing chamber, a first magnetic element positioned over a backside of the target holder, a first arm assembly connected to the first magnetic element, a rotational shaft, and a first hinge mechanism connecting the rotational shaft and the first arm assembly.

公开(公告)号：US11664308B2

公开(公告)日：2023-05-30

申请号：US17156292

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Shih Wei Bih ,  Yen-Yu Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/3105 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/02164 ,  H01L21/02252 ,  H01L21/31116 ,  H01L21/76843

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

公开(公告)号：US20230154750A1

公开(公告)日：2023-05-18

申请号：US17674575

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/40

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/0276 ,  G03F7/405

Abstract: Photoresists and methods of forming and using the same are disclosed. In an embodiment, a method includes spin-on coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, the photoresist layer being deposited using one or more organometallic precursors; heating the photoresist layer to cause cross-linking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to cause de-crosslinking in the photoresist layer forming a de-crosslinked portion of the photoresist layer; and removing the de-crosslinked portion of the photoresist layer.

公开(公告)号：US11616013B2

公开(公告)日：2023-03-28

申请号：US16900567

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Hsun Lin ,  Che-Chih Hsu ,  Wen-Chu Huang ,  Chinyu Su ,  Yen-Yu Chen ,  Wei-Chun Hua ,  Wen Han Hung

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L21/768 ,  H01L23/64

Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

公开(公告)号：US20230072507A1

公开(公告)日：2023-03-09

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US11532702B2

公开(公告)日：2022-12-20

申请号：US16877800

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.