公开(公告)号：US10825899B2

公开(公告)日：2020-11-03

申请号：US16693058

申请日：2019-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L27/108 ,  H01L27/12 ,  H01L27/11585 ,  H01L23/31 ,  H01L21/465 ,  H01L29/08 ,  H01L21/768 ,  H01L29/06 ,  H01L21/441 ,  H01L29/66 ,  H01L27/24 ,  H01L27/092 ,  H01L27/11592 ,  H01L29/778 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L21/3105 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

公开(公告)号：US10784362B2

公开(公告)日：2020-09-22

申请号：US15908348

申请日：2018-02-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US12302557B2

公开(公告)日：2025-05-13

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US12148828B2

公开(公告)日：2024-11-19

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L21/383 ,  H01L21/447 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.

公开(公告)号：US12101939B2

公开(公告)日：2024-09-24

申请号：US17883834

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US12051750B2

公开(公告)日：2024-07-30

申请号：US17884285

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11942380B2

公开(公告)日：2024-03-26

申请号：US17080625

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L29/417 ,  G01R27/26 ,  H01L21/283 ,  H01L21/306 ,  H01L21/324 ,  H01L21/66 ,  H01L29/66

CPC classification number: H01L22/14 ,  G01R27/2617 ,  H01L22/34

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

公开(公告)号：US11764267B2

公开(公告)日：2023-09-19

申请号：US17086017

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L21/465 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H10B12/00 ,  H10B51/00 ,  H10B51/40 ,  H10B63/00 ,  H01L29/10 ,  H01L23/31 ,  H01L29/51 ,  H01L29/08 ,  H01L21/768 ,  H01L29/06 ,  H01L21/441 ,  H01L27/092 ,  H01L29/778 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L21/3105 ,  H01L21/027

CPC classification number: H01L29/1033 ,  H01L21/441 ,  H01L21/465 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/3171 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/516 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78391 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78696 ,  H10B12/056 ,  H10B12/36 ,  H10B51/00 ,  H10B51/40 ,  H10B63/34 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/0273 ,  H01L21/02112 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/24

Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

公开(公告)号：US11631755B2

公开(公告)日：2023-04-18

申请号：US17179954

申请日：2021-02-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/94 ,  H01L29/51 ,  H01L29/78

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US20220384483A1

公开(公告)日：2022-12-01

申请号：US17883834

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.