公开(公告)号：US10269763B2

公开(公告)日：2019-04-23

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

公开(公告)号：US10157846B2

公开(公告)日：2018-12-18

申请号：US15292762

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

公开(公告)号：US20170194289A1

公开(公告)日：2017-07-06

申请号：US15461796

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

公开(公告)号：US20160247782A1

公开(公告)日：2016-08-25

申请号：US15143892

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.

Abstract translation: 提供机械强度和翘曲控制的封装结构的封装结构包括通过第一组导电元件耦合到第二封装元件的第一封装元件。 第一聚合物包含材料布置在第一包装部件和第二包装部件之间。 第一含聚合物的材料包围第一组导电元件和第二封装元件。 第三封装部件通过第二组导电元件耦合到第二封装部件。 底部填充物布置在第二包装部件上并且包围第二组导电元件。 第一含聚合物的材料延伸穿过底部填充物的侧壁。

公开(公告)号：US12300644B2

公开(公告)日：2025-05-13

申请号：US17841223

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chia-Li Lin ,  Yu-Chih Huang ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/00

Abstract: In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

公开(公告)号：US20240387433A1

公开(公告)日：2024-11-21

申请号：US18782141

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Po-Hao Tsai ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsu-Lun Liu ,  Kai-Di Wu ,  Su-Fei Lin

IPC: H01L23/00

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

公开(公告)号：US20240379428A1

公开(公告)日：2024-11-14

申请号：US18780044

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/60 ,  H01L23/00 ,  H01L23/532

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US12144065B2

公开(公告)日：2024-11-12

申请号：US17869384

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K3/08 ,  H01L21/677 ,  H01L21/68 ,  H01L21/683 ,  H01L23/00 ,  H05B3/02 ,  B23K101/40

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

公开(公告)号：US12107051B2

公开(公告)日：2024-10-01

申请号：US18230829

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/60

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L21/568 ,  H01L2021/6006 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20240321661A1

公开(公告)日：2024-09-26

申请号：US18679091

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Kuo-Ching Hsu ,  Wei-Hung Lin ,  Hui-Min Huang ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L23/5384 ,  H01L24/81

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.