公开(公告)号：US10522409B2

公开(公告)日：2019-12-31

申请号：US15692768

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/8234 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure also includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

公开(公告)号：US10483262B2

公开(公告)日：2019-11-19

申请号：US14714229

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Chia-Cheng Ho ,  Chih Chieh Yeh ,  Cheng-Yi Peng ,  Tsung-Lin Lee

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

公开(公告)号：US10062782B2

公开(公告)日：2018-08-28

申请号：US15429861

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chih Chieh Yeh ,  Cheng-Hsien Wu ,  Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Tsung-Lin Lee ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7853

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US10038080B1

公开(公告)日：2018-07-31

申请号：US15498727

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/306

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate over a substrate; forming at least one epitaxy structure in contact with the first dummy gate; forming a spacer layer in contact with the first dummy gate and the epitaxy structure; and replacing the first dummy gate with a metal gate stack.

公开(公告)号：US20240170341A1

公开(公告)日：2024-05-23

申请号：US18152390

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ming Chen ,  Tsung-Lin Lee ,  Chia-Ho Chu ,  Sung-En Lin ,  Sen-Hong Syue

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823857 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Semiconductor devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing a semiconductor device includes: forming first nanostructures from a first material over a substrate; forming second nanostructures from a second material different from the first material over the substrate, wherein the first nanostructures and the second nanostructures alternate vertically above the substrate; removing the first nanostructures; after the removing the first nanostructures forming an interposer in between the second nanostructures; after the forming the interposer forming a first source/drain region over the substrate and in direct physical contact with the second nanostructures; and removing the interposer exposing surfaces of each of the second nanostructures.

公开(公告)号：US20230282552A1

公开(公告)日：2023-09-07

申请号：US18196988

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L23/53271 ,  H01L23/53257 ,  H01L23/585 ,  H01L21/02532 ,  H01L29/0649 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/02595 ,  H01L23/528 ,  H01L21/76283

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US11688666B2

公开(公告)日：2023-06-27

申请号：US17336220

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US11666950B2

公开(公告)日：2023-06-06

申请号：US16886743

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Yi-Ming Lin ,  Chih-Hung Yeh ,  Zi-Yuang Wang

IPC: C23C16/00 ,  B08B3/08 ,  B08B9/08 ,  H01J37/32 ,  C23C16/44 ,  C23C16/22 ,  B05D1/00 ,  C23C14/06

CPC classification number: B08B3/08 ,  B05D1/60 ,  B08B9/08 ,  C23C14/06 ,  C23C16/00 ,  C23C16/22 ,  C23C16/4405 ,  H01J37/32862 ,  C23C16/4404

Abstract: A method of forming a process film includes the following operations. A substrate is transferred into a process chamber having an interior surface. A process film is formed over the substrate, and the process film is also formed on the interior surface of the process chamber. The substrate is transferred out of the process chamber. A non-process film is formed on the interior surface of the process chamber. In some embodiments, porosity of the process film is greater than a porosity of the non-process film.

公开(公告)号：US20220359509A1

公开(公告)日：2022-11-10

申请号：US17872348

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Chieh Hsiao ,  Johnson Chen ,  Tzung-Yi Tsai ,  Tsung-Lin Lee ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.

公开(公告)号：US20220084887A1

公开(公告)日：2022-03-17

申请号：US17021727

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung WANG ,  Tsung-Lin Lee ,  Wen-Chih Chiang ,  Kuan-Jung Chen

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3065

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.