公开(公告)号：US20160190287A1

公开(公告)日：2016-06-30

申请号：US14607085

申请日：2015-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

Abstract translation: 形成半导体器件的方法包括以下步骤。 首先，提供具有晶体管的衬底，其中晶体管包括源极/漏极区域。 在基板上形成电介质层，并且在电介质层中形成接触插塞以电连接源极/漏极区域。 接下来，在电介质层上形成掩模层，其中掩模层包括第一层和堆叠在其上的第二层。 之后，在掩模层的第二层上形成槽切割图案，并且在掩模层的第一层上形成接触槽图案。 最后，通过使用第一层上的接触槽图案，去除第二层并形成接触开口。

公开(公告)号：US09349653B2

公开(公告)日：2016-05-24

申请号：US14539225

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L21/8228 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

公开(公告)号：US20160111448A1

公开(公告)日：2016-04-21

申请号：US14519146

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/76202 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供了至少具有翅片结构的基板。 衬垫形成在翅片结构的侧壁上。 在翅片结构和基板之间形成氧化物层。 排除翅片结构，直到翅片结构的底层被保留，以在衬垫之间形成凹陷。 在凹部中依次形成缓冲外延层和外延层。 去除衬里的顶部，直到露出外延层的侧壁。 此外，还提供了通过所述方法形成的鳍状结构。

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US09287263B1

公开(公告)日：2016-03-15

申请号：US14537840

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。

公开(公告)号：US20160071844A1

公开(公告)日：2016-03-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8236

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract translation: 鳍状结构包括具有位于第一区域中的第一鳍状结构的基板和位于第二区域中的第二鳍状结构，其中第二鳍状结构包括梯形横截面轮廓部分 。 本发明还提供了形成该鳍状结构的两种方法。 在一种情况下，提供具有第一鳍状结构和第二鳍状结构的基板。 执行处理工艺以改变第二鳍状结构的顶部的外表面，从而形成修改部分。 进行去除处理以通过对第一鳍状结构和第二鳍状结构以及改性部分的高去除选择性去除改性部分，由此第二鳍状结构具有梯形横截面 形成轮廓部分。

公开(公告)号：US20160049496A1

公开(公告)日：2016-02-18

申请号：US14495907

申请日：2014-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

Abstract translation: 提供了包括栅极结构，外延隔离物和外延结构的MOS晶体管。 栅极结构设置在基板上。 除了栅极结构之外，外延衬垫设置在衬底上，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 外延结构除了外延间隔物之外还设置在基板中。 半导体工艺包括用于形成外延结构的以下步骤。 在基板上形成栅极结构。 除了用于限定外延结构的位置的栅极结构之外，在衬底上形成外延衬垫，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 该外延结构除了外延间隔物外还形成在基板中。

公开(公告)号：US20150155386A1

公开(公告)日：2015-06-04

申请号：US14620209

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US20140363935A1

公开(公告)日：2014-12-11

申请号：US13912218

申请日：2013-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

公开(公告)号：US20140295660A1

公开(公告)日：2014-10-02

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。