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    Semiconductor structure and process thereof
    51.
    发明授权
    Semiconductor structure and process thereof 有权
    半导体结构及其工艺

    公开(公告)号：US09093285B2

    公开(公告)日：2015-07-28

    申请号：US13848736

    申请日：2013-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

    IPC: H01L27/108 ,  H01L27/06 ,  H01L21/28 ,  H01L49/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

    Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

    Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

    Fin-shaped field-effect transistor (FinFET)
    54.
    发明授权
    Fin-shaped field-effect transistor (FinFET) 有权
    鳍状场效应晶体管（FinFET）

    公开(公告)号：US08981487B2

    公开(公告)日：2015-03-17

    申请号：US13954991

    申请日：2013-07-31

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Po-Chao Tsao ,  Chung-Fu Chang ,  Cheng-Guo Chen

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/1211 ,  H01L21/845

    Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

    Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板中形成翅片状结构; 在衬底上并在鳍状结构的底部周围形成浅沟槽隔离（STI）; 在STI和鳍状结构上形成第一栅极结构; 以及去除STI的一部分以暴露在第一栅极结构下方的STI的侧壁。

    Method for fabricating patterned structure of semiconductor device
    55.
    发明授权
    Method for fabricating patterned structure of semiconductor device 有权
    制造半导体器件图案化结构的方法

    公开(公告)号：US08951918B2

    公开(公告)日：2015-02-10

    申请号：US13851113

    申请日：2013-03-27

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

    IPC: H01L21/311 ,  H01L21/308

    CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

    Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

    Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

    METHOD OF FORMING FIN-SHAPED STRUCTURE
    56.
    发明申请
    METHOD OF FORMING FIN-SHAPED STRUCTURE 有权
    形成精细结构的方法

    公开(公告)号：US20140349482A1

    公开(公告)日：2014-11-27

    申请号：US13902970

    申请日：2013-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Chien-Ting Lin

    IPC: H01L21/306 ,  H01L21/311 ,  H01L21/304

    CPC classification number: H01L21/3086 ,  H01L21/76224 ,  H01L29/66795

    Abstract: A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts.

    Abstract translation: 形成鳍状结构的方法包括以下步骤。 在基板上形成多个间隔物。 通过使用间隔物作为硬掩模来蚀刻衬底，以在衬底中形成多个鳍状结构。 然后进行切割过程以去除鳍状结构的部分和形成在去除部分上的间隔物。

    REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME
    57.
    发明申请
    REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME 有权
    更换浇口工艺和使用其制造的装置

    公开(公告)号：US20140327055A1

    公开(公告)日：2014-11-06

    申请号：US13886382

    申请日：2013-05-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

    Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

    Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG
    58.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG 有权
    形成具有接触片的半导体结构的方法

    公开(公告)号：US20140199837A1

    公开(公告)日：2014-07-17

    申请号：US13740289

    申请日：2013-01-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

    IPC: H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

    Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

    Semiconductor integrated circuit
    60.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US09548302B2

    公开(公告)日：2017-01-17

    申请号：US14681081

    申请日：2015-04-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao

    IPC: H01L27/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

    Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

    Abstract translation: 半导体集成电路包括衬底，形成在衬底上的多栅极晶体管器件和形成在衬底中的n阱电阻器。 衬底包括多个第一隔离结构和至少形成在其中的第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个翅片结构，并且翅片结构彼此平行并且通过第一隔离结构彼此间隔开。 n阱电阻器包括至少一个第一隔离结构。 n阱电阻器和多栅极晶体管器件通过第二隔离结构彼此电隔离。

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