公开(公告)号：US20070128845A1

公开(公告)日：2007-06-07

申请号：US11408072

申请日：2006-04-21

申请人： Yung-Yu Hsu ,  Chih-Yuan Chen ,  Shyi-Ching Liau ,  Min-Lin Lee ,  Ra-Min Tain ,  Rong-Chang Feng

发明人： Yung-Yu Hsu ,  Chih-Yuan Chen ,  Shyi-Ching Liau ,  Min-Lin Lee ,  Ra-Min Tain ,  Rong-Chang Feng

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L24/12 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/81899 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/326 ,  H05K2201/0373 ,  H05K2201/209 ,  H01L2924/00

摘要： An interconnect structure of an integrated circuit and manufacturing method therefor are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.

摘要翻译： 提供了一种集成电路的互连结构及其制造方法，涉及柔性封装的互连结构。 互连结构包括第一和第二导电焊盘。 多个微小且导电的第一支柱分别形成在第一和第二垫上。 当第一和第二支柱具有不同的密度和厚度时，当支柱互相连接时，可以产生接触强度，使得支柱紧密连接。 此外，互连结构也可以用于与由导电材料制成的纤维连接。 此外，支柱的密度越高，接触强度越强。 并且，电子基板和有源或无源电子元件可以卡在每个垫的另一侧上。 因此，互连结构可以保持柔性并且具有高可靠性，而不会被任何热固性聚合物增强。

公开(公告)号：US07894178B2

公开(公告)日：2011-02-22

申请号：US12046422

申请日：2008-03-11

申请人： Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

发明人： Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

IPC分类号： H01G9/04 ,  H01G9/145 ,  H01G4/228

CPC分类号： H05K1/162 ,  H01G9/012 ,  H01G11/48 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y02E60/13 ,  Y10T29/417 ,  Y10T29/435

摘要： A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission.

摘要翻译： 提供至少包括基板，阳极层，电介质层，第一阴极层和第二阴极层的通孔电容器。 基板具有多个通孔。 阳极层设置在至少一个通孔的内表面上，阳极层的表面是多孔结构。 电介质层设置在阳极层的多孔结构上。 第一阴极层覆盖电介质层的表面。 第二阴极层覆盖第一阴极层的表面，第二阴极层的导电性大于第一阴极层的导电率。 通孔电容器可用于阻抗控制，因为通孔的阴极层用于信号传输。

公开(公告)号：US20090210055A1

公开(公告)日：2009-08-20

申请号：US12211829

申请日：2008-09-17

申请人： Tao-Chih Chang ,  Min-Lin Lee

发明人： Tao-Chih Chang ,  Min-Lin Lee

IPC分类号： A61F2/14

CPC分类号： A61F9/08 ,  A61F2/141 ,  A61N1/36046

摘要： An artificial retina chip module including a signal processing chip, a first polymer bump layer, and a photodiode array chip is provided. The signal processing chip includes a plurality of first pad disposed on a surface thereof. The first polymer bump layer includes a plurality of polymer bumps insulated from one another. Each of the first polymer bumps is composed of a polymer material and a conductive layer coated on the polymer material. Each first polymer bump is embedded into the corresponding first pad and the signal processing chip, wherein one end of the first polymer bump protrudes from the first pad and the other end thereof protrudes from a back surface of the signal processing chip. The photodiode array chip is disposed at one side of the signal processing chip and is electrically connected to the signal processing chip through the first polymer bumps.

摘要翻译： 提供了包括信号处理芯片，第一聚合物凸块层和光电二极管阵列芯片的人造视网膜芯片模块。 信号处理芯片包括设置在其表面上的多个第一焊盘。 第一聚合物凸块层包括彼此绝缘的多个聚合物凸块。 每个第一聚合物凸块由聚合物材料和涂覆在聚合物材料上的导电层组成。 每个第一聚合物凸块被嵌入到相应的第一焊盘和信号处理芯片中，其中第一聚合物凸块的一端从第一焊盘凸出并且另一端从信号处理芯片的后表面突出。 光电二极管阵列芯片设置在信号处理芯片的一侧，并通过第一聚合物凸块与信号处理芯片电连接。

公开(公告)号：US07893359B2

公开(公告)日：2011-02-22

申请号：US11470435

申请日：2006-09-06

申请人： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chih-Hao Chang

发明人： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chih-Hao Chang

IPC分类号： H05K1/16 ,  H05K1/18

CPC分类号： H05K1/162 ,  H05K3/4611 ,  H05K2201/0209 ,  H05K2201/09309 ,  Y10T29/43 ,  Y10T29/49126

摘要： An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.

摘要翻译： 一种嵌入式电容器芯，包括第一组电容器，第二组电容器和在第一组电容器和第二组电容器之间的层间电介质膜。 第一组电容器包括：包括至少两个导电电极的第一导电图案; 第二导电图案，包括对应于第一导电图案的两个导电电极的至少两个导电电极; 以及在第一导电图案和第二导电图案之间的第一电介质膜。 第二组电容器包括：包括至少两个导电电极的第三导电图案; 第四导电图案，包括对应于第三导电图案的两个导电电极的至少两个导电电极; 以及在第三导电图案和第四导电图案之间的第二电介质膜。

公开(公告)号：US07561410B1

公开(公告)日：2009-07-14

申请号：US12050188

申请日：2008-03-18

申请人： Min-Lin Lee ,  Li-Duan Tsai ,  Shur-Fen Liu ,  Bang-Hao Wu ,  Cheng-Liang Cheng

发明人： Min-Lin Lee ,  Li-Duan Tsai ,  Shur-Fen Liu ,  Bang-Hao Wu ,  Cheng-Liang Cheng

IPC分类号： H01G9/025

CPC分类号： H01G9/15 ,  H01G9/0029 ,  H01G9/012 ,  H01L23/642 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/19015 ,  H01L2924/3011 ,  H01L2924/00

摘要： A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer.

摘要翻译： 提供了一种混合电容器，其包括基板，至少一个平板电容器和至少一个通孔电容器。 衬底具有通孔，并且板电容器在衬底上。 至少一个通孔电容器和至少一个平板电容器是并联的。 通孔电容器至少包括阳极层，第一电介质层，第一阴极层和第二阴极层。 阳极层设置在至少一个通孔的内表面上，阳极层的表面是多孔结构。 第一介电层设置在阳极层的多孔结构上并被第一阴极层覆盖。 第一阴极层被第二阴极层覆盖。 第二阴极层的导电率大于第一阴极层的导电率。

公开(公告)号：US20070164395A1

公开(公告)日：2007-07-19

申请号：US11308493

申请日：2006-03-30

申请人： Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

发明人： Jiin-Shing Perng ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC分类号： H01L29/00

CPC分类号： H01L23/642 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49589 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the first metal foil and the second metal foil. The carrier is disposed on the surface away from the dielectric layer of the second metal foil. The first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil. The molding compound is disposed on the carrier for fixing the IC unit, the capacitor unit and the carrier.

摘要翻译： 提供具有集成电路（IC）单元，电容器单元，载体和模塑料的内置电容器结构的芯片封装。 电容器单元设置在IC单元上，并且包括第一金属箔，第二金属箔和设置在第一金属箔和第二金属箔之间的电介质层。 载体设置在远离第二金属箔的电介质层的表面上。 第一金属箔与载体电连接，第二金属箔电连接到载体上，IC单元与载体电连接，IC单元电连接到第一金属箔，并且IC单元电气 连接到第二金属箔。 模制化合物设置在载体上用于固定IC单元，电容器单元和载体。

公开(公告)号：US20060285273A1

公开(公告)日：2006-12-21

申请号：US11156350

申请日：2005-06-17

申请人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

发明人： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC分类号： H01G4/20

CPC分类号： H05K1/024 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0298 ,  H05K3/386 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09881 ,  H01L2924/00

摘要： This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.

摘要翻译： 本发明公开了一种复合分布介质结构。 它包括一个或多个导体层，分布在导体层上的一个或多个电介质层，以及分布在电介质层上的一个或多个导体迹线。 一个或多个电介质板可以进一步围绕导体迹线。 在两个实施例中分别描述了介电层或板可以具有或可以不具有多个电介质材料。 每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。 两个或多个电介质层可以堆叠在导体层上本发明为互连系统提供了一种低成本和实用的电介质结构，以减少介质损耗，串扰和信号传播延迟，并且在保持适当的散热的同时良好地控制阻抗匹配， 高频传输降噪。

公开(公告)号：US06683781B2

公开(公告)日：2004-01-27

申请号：US10152669

申请日：2002-05-23

申请人： Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

发明人： Ted C. Ho ,  Min-Lin Lee ,  Huey-Ru Chang ,  Shinn-Juh Lay

IPC分类号： H01G400

CPC分类号： H01L23/642 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A packaging structure with low switching noises is disclosed. In this structure, a chip capacitor is connected to a chip. The chip capacitor is a capacitor structure formed using a high dielectric material to provide a better noise filtering effect. Therefore, the invention can effectively lower switching noises.

摘要翻译： 公开了一种具有低开关噪声的封装结构。 在该结构中，芯片电容器连接到芯片。 片式电容器是使用高介电材料形成的电容器结构，以提供更好的噪声滤波效果。 因此，本发明可以有效地降低开关噪声。

公开(公告)号：US09030808B2

公开(公告)日：2015-05-12

申请号：US13607820

申请日：2012-09-10

申请人： Chien-Min Hsu ,  Min-Lin Lee ,  Li-Duan Tsai

发明人： Chien-Min Hsu ,  Min-Lin Lee ,  Li-Duan Tsai

IPC分类号： H01G5/38 ,  H01G9/04 ,  H05K1/16 ,  H01G9/012 ,  H01G9/15 ,  H01G9/26 ,  H05K1/02 ,  H05K1/05

CPC分类号： H05K1/162 ,  H01G9/012 ,  H01G9/04 ,  H01G9/15 ,  H01G9/26 ,  H05K1/0231 ,  H05K1/053 ,  H05K2201/0116 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2201/0338 ,  H05K2201/09063 ,  H05K2201/10522 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/0723

摘要： A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.

摘要翻译： 提供电容器和具有该电容器的电路板。 电容器包括衬底，氧化物层，第二电极，绝缘层，多个导电片和多个通孔。 基板包括第一电极和多孔结构。 至少两个分布区域中的多孔结构具有不同的深度。 氧化物层设置在多孔结构的表面上。 第二电极设置在氧化物层上并且包括导电聚合物材料。 设置在第二电极上的绝缘层具有第三和第四表面。 绝缘层的第四表面与第二电极连接。 导电片设置在第一电极的第一表面和绝缘层的第三表面上，并根据不同的极性与相应的通孔电连接。

公开(公告)号：US20120168217A1

公开(公告)日：2012-07-05

申请号：US13197283

申请日：2011-08-03

申请人： Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

发明人： Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

IPC分类号： H05K1/16

CPC分类号： H05K1/0231 ,  H01G9/012 ,  H01G9/15 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2203/0315

摘要： An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.

摘要翻译： 嵌入式电容器基板模块包括基板，金属基板和固体电解电容器材料。 在金属基板上形成固体电解电容器材料，以便与基板形成固体电解电容器。 嵌入式电容器基板模块还包括通过使基板和金属基板延伸而形成的电极引出区域。 金属基板用作第一电极，并且基板用作第二电极。 在基板和金属基板之间形成绝缘材料。 因此，嵌入式电容器基板模块不仅有利于具有作为常规固体电容器的大电容，而且还可以在嵌入印刷电路板中之后被钻孔或电镀并电连接到其它电路。