利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

69 条记录 (耗时 0.016 秒)

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    53.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 审中-公开
    半导体结构的制造方法

    公开(公告)号：US20150214114A1

    公开(公告)日：2015-07-30

    申请号：US14166091

    申请日：2014-01-28

    申请人： United Microelectronics Corp.

    发明人： Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chun-Hsiung Wang ,  Kun-Ju Li ,  Chia-Lin Hsu ,  Chih-Chien Liu

    IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/321

    CPC分类号： H01L21/823437 ,  H01L21/31051 ,  H01L21/31055 ,  H01L29/66545

    摘要： A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

    摘要翻译： 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供具有形成在其上的多个虚拟栅极结构的基板和覆盖该虚拟栅极结构的第一介电层，所述伪栅极结构包括形成在所述伪栅极上的多个伪栅极和多个绝缘层，其中至少两个 的虚拟门结构具有不同的高度。 执行第一平面化处理以暴露具有最高高度的虚拟栅极结构中的至少一个。 执行第一蚀刻工艺以暴露绝缘层。 进行具有非选择性浆料的化学机械抛光（CMP）工艺以使虚拟栅极结构平坦化。 平面化的虚拟栅极结构被去除以形成多个栅极沟槽。

    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS
    57.
    发明申请
    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS 有权

    公开(公告)号：US20220084878A1

    公开(公告)日：2022-03-17

    申请号：US17023391

    申请日：2020-09-17

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/3105

    摘要： A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

    Alignment mark structure and method of fabricating the same
    59.
    发明授权
    Alignment mark structure and method of fabricating the same 有权

    公开(公告)号：US11145602B2

    公开(公告)日：2021-10-12

    申请号：US16786919

    申请日：2020-02-10

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    摘要： An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.