公开(公告)号：US20060180880A1

公开(公告)日：2006-08-17

申请号：US11060000

申请日：2005-02-17

申请人： Chao-Hsiung Wang ,  Horng-Huei Tseng ,  Denny Tang

发明人： Chao-Hsiung Wang ,  Horng-Huei Tseng ,  Denny Tang

IPC分类号： H01L29/82

CPC分类号： H01L23/552 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2224/0401

摘要： A magnetic shielding device is provided for protecting at least one magnetically sensitive component on a substrate according to embodiments of the present invention. The device comprises a first shield having a top portion, and one or more side portions, wherein the top and side portions along with the substrate encloses the magnetic sensitive component within for protecting the same from an external magnetic field, and wherein the magnetic shielding device contains at least two magnetic shielding materials with one having a relatively higher magnetic permeability property but lower magnetic saturation property while the other having a relatively lower magnetic permeability property but higher magnetic saturation property.

摘要翻译： 根据本发明的实施例，提供了一种磁屏蔽装置，用于保护基板上的至少一个磁敏部件。 该装置包括具有顶部部分和一个或多个侧部部分的第一屏蔽件，其中顶部和侧部与基板一起包围磁敏部件，以便将其与外部磁场保护起来，并且其中磁屏蔽装置 包含至少两个磁屏蔽材料，具有较高磁导率性能但具有较低磁饱和性能的磁屏蔽材料，而另一种具有较低的磁导率性能但较高的磁饱和性能。

公开(公告)号：US20060148229A1

公开(公告)日：2006-07-06

申请号：US11028841

申请日：2005-01-04

申请人： Chao-Hsiung Wang ,  Li-Shyue Lai ,  Denny Tang ,  Wen-Chen Lin

发明人： Chao-Hsiung Wang ,  Li-Shyue Lai ,  Denny Tang ,  Wen-Chen Lin

IPC分类号： H01L21/3205

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/165 ,  H01L45/1666

摘要： A method of manufacturing a memory device including forming an electrode over a substrate, then forming a dielectric feature proximate a contact region of a sidewall of the electrode, and then forming a phase change feature proximate the contact region.

摘要翻译： 一种制造存储器件的方法，包括在衬底上形成电极，然后在电极的侧壁的接触区域附近形成电介质特征，然后在接触区域附近形成相变特征。

公开(公告)号：US07016029B2

公开(公告)日：2006-03-21

申请号：US10167162

申请日：2002-06-11

申请人： Hung-Chih Chen ,  Chao-Hsiung Wang ,  Niahn-Mauh Shih ,  Hsien-Wei Chin

发明人： Hung-Chih Chen ,  Chao-Hsiung Wang ,  Niahn-Mauh Shih ,  Hsien-Wei Chin

IPC分类号： G01N21/00

CPC分类号： G03F7/7065 ,  G01N21/47 ,  G01N21/9501 ,  G03F7/70808 ,  G03F7/70941 ,  G03F7/70958

摘要： Detecting decay of equipment lens anti-reflective coating (ARC) by detecting undesired residue is disclosed. The undesired residue detected correlates with the decay of the ARC, where a greater amount of undesired residue detected indicates a greater level of the decay. The undesired residue is detected due to stray light reflected by the ARC because of its decay. In the context of semiconductor fabrication equipment, photoresist residue results from negative photoresist on a semiconductor wafer, and may be viewed on one or more scribe lines of a mask within a field of view of the lens of the semiconductor fabrication equipment.

公开(公告)号：US20050272260A1

公开(公告)日：2005-12-08

申请号：US10861149

申请日：2004-06-04

申请人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US20050133817A1

公开(公告)日：2005-06-23

申请号：US10710012

申请日：2004-06-11

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/76

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

摘要翻译： 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US20050110147A1

公开(公告)日：2005-05-26

申请号：US10723509

申请日：2003-11-25

申请人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

发明人： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

摘要翻译： 铜填充镶嵌结构及其形成方法，包括提供包括半导体衬底的衬底; 在所述基板上形成绝缘体层; 通过所述绝缘体层的厚度部分形成镶嵌开口; 形成扩散阻挡层以使所述镶嵌开口成线; 形成覆盖所述扩散阻挡层的第一晶种层; 用包含选自氩，氮，氢和NH 3的等离子体源气体的第一处理等离子体原位处理第一籽晶层; 形成覆盖所述第一种子层的第二种子层; 根据电化学电镀（ECP）工艺形成覆盖在第二晶种层上的铜层以填充镶嵌开口; 并且平坦化铜层以形成金属互连结构。

公开(公告)号：US06878610B1

公开(公告)日：2005-04-12

申请号：US10228545

申请日：2002-08-27

申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/36 ,  H01L21/84 ,  H01L29/10

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.

摘要翻译： 已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。 在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。 在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。 第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理 允许为SiGe层实现优化的弛豫和缺陷密度。 在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的， 低缺陷密度SiGe层。

公开(公告)号：US09318431B2

公开(公告)日：2016-04-19

申请号：US13289666

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L23/522 ,  H01L29/94 ,  H01L29/40 ,  H01L49/02 ,  H01L27/12

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

摘要翻译： 集成电路可以包括与其它器件（例如finFET）同时形成的MOM电容器。 形成在基板上的电介质层具有第一半导体鳍片和第二半导体鳍片。 除去翅片的各顶部以形成电介质层中的相应凹部。 第一和第二电极形成在凹槽中。 第一和第二电极和中间介电层形成MOM电容器。

公开(公告)号：US08604498B2

公开(公告)日：2013-12-10

申请号：US12732437

申请日：2010-03-26

申请人： Hsin-Chieh Huang ,  Chao-Hsiung Wang

发明人： Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC分类号： H01L33/00

CPC分类号： H01L33/502 ,  H01L27/153 ,  H01L33/0079 ,  H01L33/382 ,  H01L33/504 ,  H01L33/508 ,  H01L33/62 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A photonic device generates light from a full spectrum of lights including white light. The device includes two or more LEDs grown on a substrate, each generating light of a different wavelength and separately controlled. A light-emitting structure is formed on the substrate and apportioned into the two or more LEDs by etching to separate the light-emitting structure into different portions. At least one of the LEDs is coated with a phosphor material so that different wavelengths of light are generated by the LEDs while the same wavelength of light is emitted from the light-emitting structure.

公开(公告)号：US08564018B2

公开(公告)日：2013-10-22

申请号：US12038091

申请日：2008-02-27

申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

IPC分类号： H01L21/02

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

摘要： A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

摘要翻译： 公开了一种用于集成电路的结构。 该结构包括晶体衬底和四个结晶层。 第一晶格常数的第一晶体层位于晶体衬底上。 第二晶体层具有不同于第一晶格常数的第二晶格常数，并且位于所述第一晶体层上。 第三晶体层具有与所述第二晶格常数不同的第三晶格常数，并且位于所述第二晶体层上。 应变的第四晶体层至少部分地包括MOSFET器件。