公开(公告)号：US6088291A

公开(公告)日：2000-07-11

申请号：US147600

申请日：1999-01-29

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

公开(公告)号：US5986293A

公开(公告)日：1999-11-16

申请号：US931935

申请日：1997-09-17

申请人： Takaaki Suzuki ,  Hirohiko Mochizuki ,  Masao Taguchi

发明人： Takaaki Suzuki ,  Hirohiko Mochizuki ,  Masao Taguchi

IPC分类号： G05F1/46 ,  H01L20060101 ,  H01L27/105 ,  H01L27/10

CPC分类号： G05F1/465

摘要： A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.

摘要翻译： 一种半导体集成电路器件，包括从升压电压输出参考电压的基准电压产生电路，在比外部电源电压低的范围内升压参考电压的升压电路，从而输出上述升压 电压，降压电路降低外部电源电压，从而输出等于参考电压的降压电压，内部电路作为其电源电压接收降压电压。

公开(公告)号：US5767712A

公开(公告)日：1998-06-16

申请号：US892066

申请日：1997-07-14

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  H03L7/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间 信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US5729154A

公开(公告)日：1998-03-17

申请号：US715358

申请日：1996-09-10

申请人： Masao Taguchi ,  Tsuyoshi Higuchi

发明人： Masao Taguchi ,  Tsuyoshi Higuchi

IPC分类号： G06F13/40 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03K17/16 ,  H03K19/0175

CPC分类号： H04L25/028 ,  H03K19/00384 ,  H03K19/018571 ,  H04L25/0278 ,  H04L25/0298 ,  H04L25/0266 ,  H04L25/0292

摘要： An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.

公开(公告)号：US5544109A

公开(公告)日：1996-08-06

申请号：US205361

申请日：1994-03-03

申请人： Toshiya Uchida ,  Masao Taguchi

发明人： Toshiya Uchida ,  Masao Taguchi

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： A semiconductor memory device includes a flip-flop circuit, a switch provided between the flip-flop circuit and a pair of data lines, a write circuit writing data into the flip-flop circuit via the switch, and a circuit applying a predetermined voltage to the pair of data lines when the write circuit performs a write operation so that a voltage amplitude on the pair of data lines is limited so as to be less than a voltage amplitude of the flip-flop circuit in the write operation.

摘要翻译： 半导体存储器件包括触发器电路，设置在触发器电路和一对数据线之间的开关，写入电路经由开关将数据写入触发器电路，以及将预定电压施加到 当写入电路执行写入操作以使得该对数据线上的电压幅度被限制为小于写入操作中触发器电路的电压幅度时，该对数据线。

公开(公告)号：US5465220A

公开(公告)日：1995-11-07

申请号：US69853

申请日：1993-06-01

申请人： Tamae Haruki ,  Kenji Nakagawa ,  Masao Taguchi ,  Hiroyuki Tanaka ,  Satoru Asai ,  Isamu Hanyu

发明人： Tamae Haruki ,  Kenji Nakagawa ,  Masao Taguchi ,  Hiroyuki Tanaka ,  Satoru Asai ,  Isamu Hanyu

IPC分类号： G03F7/20 ,  G03F7/207 ,  G06F9/00

CPC分类号： G03F7/70566 ,  G03F7/201 ,  G03F7/70091 ,  G03F7/701 ,  G03F7/70125 ,  G03F7/70241 ,  G03F7/70283 ,  G03F7/70583

摘要： An optical exposure method in photolithography applied for precise processing when semiconductor devices are produced. A pattern on a photomask is projected and exposed on a register on a base plate with an exposure device including a deformation illumination system, a photomask and a projection lens. The deformation illumination system is composed of a light source, a diaphragm and a condenser lens, and the diaphragm is provided with a linear through-hole. The optical exposure method uses a ray of linear light for illumination or two rays of linear light for illumination that are parallel with the pattern. The two rays of linear light are symmetrical with respect to an optical axis. These rays are parallel with the pattern in a position separate from the optical axis of the exposure device when the photomask pattern is a line and space pattern.

公开(公告)号：US5175128A

公开(公告)日：1992-12-29

申请号：US789192

申请日：1991-11-08

申请人： Taiji Ema ,  Hisatsugu Shirai ,  Katsuyoshi Kobayashi ,  Masao Taguchi

发明人： Taiji Ema ,  Hisatsugu Shirai ,  Katsuyoshi Kobayashi ,  Masao Taguchi

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L28/87 ,  H01L21/0274 ,  H01L21/76802 ,  Y10S438/946

摘要： A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions on a substrate, exposing a first pattern that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.

公开(公告)号：US5152900A

公开(公告)日：1992-10-06

申请号：US651941

申请日：1991-02-07

申请人： Kazuya Sekiguchi ,  Masao Taguchi ,  Masayuki Nakatani ,  Tomoyuki Seki ,  Takaaki Shimizu ,  Mahito Orii

发明人： Kazuya Sekiguchi ,  Masao Taguchi ,  Masayuki Nakatani ,  Tomoyuki Seki ,  Takaaki Shimizu ,  Mahito Orii

IPC分类号： A61L2/02 ,  B65B55/12

CPC分类号： B65B55/12 ,  A61L2/022

摘要： Sterilized and packaged mineral water comprises sterilized mineral water having a hardness of not less than 50 mg/l and a content of dissolved carbonic acid gas ranging from 9 to 30 mg/l (as calcium carbonate) and a number of bacteria of not more than 10.sup.-3 /ml which is obtained by sterilizing pumped-up mineral water having a hardness of not less than 50 mg/l and a content of dissolved carbonic acid gas ranging from 10 to 31 mg/l by filtering through a filter having a pore size of not more than 0.22 .mu.m. The packaged and sterilized mineral water can be effectively prepared by a method which comprises packaging pumped-up mineral water in a container without subjecting it to any heat-sterilization treatment wherein the mineral water is sterilized by passing through a filter having a pore size of not more than 0.22 .mu.m, packaged in a sterilized container under an aseptic condition of not more than Class 100 and then the container is airtight-sealed. Thus, packaged and sterilized mineral water having excellent keeping quality can be obtained without subjecting pumped-up mineral water to any sterilization by heating and without using any antibacterial agent and it has a high hardness and a high carbon dioxide content as well as good taste peculiar to the original mineral water.

公开(公告)号：US5071783A

公开(公告)日：1991-12-10

申请号：US376470

申请日：1989-07-05

申请人： Masao Taguchi ,  Taiji Ema

发明人： Masao Taguchi ,  Taiji Ema

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on a lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

摘要翻译： 动态随机存取存储器件包括具有形成存储电极的多个层叠导电膜的存储电容器。 在垂直相邻的导电膜之间形成间隙以包围存储电极。 在覆盖用于绝缘的栅电极的绝缘膜和存储电极的最下面的膜之间也形成间隙。 可以建立相邻膜之间的连接，使得最上面的膜垂直地延伸以与漏区接触。 此外，可以建立连接，使得上部膜直接安装在下部膜上。 膜的端部可以比其它部分厚。 层叠膜结构可以通过交替地形成由与覆盖栅电极的绝缘膜不同的材料制成的膜和导电膜来制造。

公开(公告)号：US5006910A

公开(公告)日：1991-04-09

申请号：US222305

申请日：1988-07-21

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A semiconductor memory device having a semiconductor substrate includes; a field oxide layer selectively formed on the semiconductor substrate, and a capacitor including an insulating layer formed on the surface of a trench formed in such a manner that at least an edge portion of the field oxide layer is removed. A conductive layer is formed on the insulating layer, a dielectric layer is formed on the conductive layer and an electrode is formed on the dielectric layer.

摘要翻译： 具有半导体衬底的半导体存储器件包括： 选择性地形成在半导体衬底上的场氧化物层，以及形成在沟槽表面上的绝缘层的电容器，其形成为至少除去场氧化物层的边缘部分。 在绝缘层上形成导电层，在导电层上形成电介质层，在电介质层上形成电极。