公开(公告)号：US08847335B2

公开(公告)日：2014-09-30

申请号：US13597044

申请日：2012-08-28

Applicant: Shian-Yeu Kam ,  Tien-Choy Loh ,  Ying Yu ,  Fery Riswan ,  Frederic Sala

Inventor： Shian-Yeu Kam ,  Tien-Choy Loh ,  Ying Yu ,  Fery Riswan ,  Frederic Sala

IPC: H01L27/14 ,  B82Y40/00 ,  G01N27/74 ,  G01R33/09 ,  G11B5/39

CPC classification number: B82Y40/00 ,  B81B3/0072 ,  B81B2201/0214 ,  B81B2203/0127 ,  B81C2201/0167 ,  G01R33/093 ,  G01R33/098 ,  G01R33/16

Abstract: A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void.

Abstract translation: 微电化学传感器包含插入在衬底内的磁性化合物，其在与电极保持接触的顺磁珠上施加吸引力。 磁性化合物可以包含在引入基底中的空隙的流体中。 电极可以通过电介质多层膜与磁性化合物间隔开。 在制造过程中，可以调整膜 - 电极结构内的不同层以具有压缩或拉伸应力，以便保持膜的结构完整性，与其下方的空隙尺寸相比较薄。 在形成传感器的结构的过程中，可以调节TiW粘合层中的拉伸应力以抵消与膜的电介质层相关联的复合网压应力。 膜也可以用于形成电极和空隙。

公开(公告)号：US08822267B2

公开(公告)日：2014-09-02

申请号：US13655036

申请日：2012-10-18

Applicant: STMicroelectronics Pte Ltd.

Inventor： How Yuan Hwang ,  Jay Maghirang ,  Yaohuang Huang ,  Kim-Yong Goh ,  Phone Maw Hla ,  Edmond Soon

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.

Abstract translation: 本公开的实施例涉及在晶片级制造系统级封装。 具体地，各种实施例涉及将第一晶片粘附到第二晶片并将焊球粘附到第一晶片的接触焊盘。 在一个实施例中，提供具有第一和第二表面的第一晶片。 第一晶片包括位于第一表面上的接合焊盘，其耦合到位于第一晶片中的相应半导体器件。 提供了具有位于其中的电气部件的第二晶片。 在第一晶片和第二晶片中的至少一个上提供导电粘合剂。 导电球设置在第一晶片的第一表面上的接合焊盘上。 导电球和导电粘合剂被加热以使导电球粘附到接合焊盘和导电粘合剂以将第一晶片粘附到第二晶片。

公开(公告)号：US08728831B2

公开(公告)日：2014-05-20

申请号：US12982707

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yonggang Jin

IPC: H01L21/00

CPC classification number: H01L21/67288

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract translation: 一种减少半导体晶片翘曲的系统和方法。 该系统包括用于将半导体晶片固定在加热区域中的装置。 该装置包括用于固定半导体晶片的边缘的保持机构。 该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。 加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

公开(公告)号：US08722545B2

公开(公告)日：2014-05-13

申请号：US13595933

申请日：2012-08-27

Applicant: Hong-Gap Chua ,  Yee-Chung Chan ,  Mei-Yu Muk

Inventor： Hong-Gap Chua ,  Yee-Chung Chan ,  Mei-Yu Muk

IPC: H01L21/302 ,  H01L21/22

CPC classification number: H01L29/66575 ,  H01L21/2255 ,  H01L29/78

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract translation: 公开了一种形成晶体管的方法，其中通过形成和维持覆盖晶体管栅极的共形氧化物层来解决栅极到衬底的泄漏。 使用公开的用于n型器件的方法，保形氧化物层可以形成为源 - 漏掺杂工艺的一部分。 随后从氧化物层的表面除去残留的磷掺杂剂，而不会明显地侵蚀氧化物层。 除去步骤使用采用水解反应的选择性脱气方法和包含氢氧化铵组分的酸碱中和反应。

公开(公告)号：US20140061823A1

公开(公告)日：2014-03-06

申请号：US13597044

申请日：2012-08-28

Applicant: Shian-Yeu Kam ,  Tien-Choy Loh ,  Ying Yu ,  Fery Riswan ,  Frederic Sala

Inventor： Shian-Yeu Kam ,  Tien-Choy Loh ,  Ying Yu ,  Fery Riswan ,  Frederic Sala

IPC: H01L29/66 ,  H01L21/02

CPC classification number: B82Y40/00 ,  B81B3/0072 ,  B81B2201/0214 ,  B81B2203/0127 ,  B81C2201/0167 ,  G01R33/093 ,  G01R33/098 ,  G01R33/16

Abstract: A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void.

Abstract translation: 微电化学传感器包含插入在衬底内的磁性化合物，其在与电极保持接触的顺磁珠上施加吸引力。 磁性化合物可以包含在引入基底中的空隙的流体中。 电极可以通过电介质多层膜与磁性化合物间隔开。 在制造过程中，可以调整膜 - 电极结构内的不同层以具有压缩或拉伸应力，以便保持膜的结构完整性，与其下方的空隙尺寸相比较薄。 在形成传感器的结构的过程中，可以调节TiW粘合层中的拉伸应力以抵消与膜的电介质层相关联的复合网压应力。 膜也可以用于形成电极和空隙。

公开(公告)号：US20140000804A1

公开(公告)日：2014-01-02

申请号：US13539994

申请日：2012-07-02

Applicant: Han Kong Looi ,  Cheng-hai Cheh

Inventor： Han Kong Looi ,  Cheng-hai Cheh

IPC: B32B38/18 ,  B32B37/12

CPC classification number: H01L24/83 ,  H01L24/75 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/75263 ,  H01L2224/75745 ,  H01L2224/82214 ,  H01L2224/83192 ,  H01L2224/83874

Abstract: A pick and place system with an integrated light source to partially cure a light-curable adhesives onto which components have been placed. After a light-curable adhesive in liquid or low viscosity form is applied to a location on a substrate, a pick-and-place head uses a vacuum introduced to its nozzle-like opening to pick a component and place it on to the light-curable adhesive. The pick-and-place head then transmit an appropriate light through the same nozzle-like opening to at least partially cure the adhesive. The component becomes, therefore, at least partially fixed to the substrate and will not shift as the substrate is moved.

Abstract translation: 具有集成光源的拾取和放置系统，用于部分固化已经放置组件的可光固化粘合剂。 将液体或低粘度形式的可光固化粘合剂施加到基板上的位置之后，拾取头使用引入其喷嘴状开口的真空来挑选部件并将其放置在发光元件上， 可固化粘合剂。 拾取头然后通过相同的喷嘴状开口传递适当的光以至少部分地固化粘合剂。 因此，该部件至少部分地固定到基板上，并且将不会随着基板移动而移动。

公开(公告)号：US08576574B2

公开(公告)日：2013-11-05

申请号：US12764704

申请日：2010-04-21

Applicant: Wingshenq Wong ,  David Gani ,  Glenn De Los Reyes

Inventor： Wingshenq Wong ,  David Gani ,  Glenn De Los Reyes

IPC: H05K1/18

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00

Abstract: A conductive paint electromagnetic interference (EMI) shield for an electronic module or device. The conductive paint is composed of metal particles suspended in a fluidic carrier. In one embodiment, the conductive paint is sprayed onto exterior surfaces of an electronic module or device from a spray gun. The sprayed conductive paint is cured to remove the fluidic carrier, leaving a metal film coated to the outside of the module or device. In one embodiment used with electronic packages in array form, grooves are cut into an encapsulation material of a module so that the shield protection includes sidewalls of the package. In another embodiment used with camera modules, masking is used to selectively shield portions of the module. In a further embodiment, the shield is electrically connected to a ground conductor of a circuit of the electronic module.

Abstract translation: 电子模块或设备的导电油漆电磁干扰（EMI）屏蔽。 导电涂料由悬浮在流体载体中的金属颗粒组成。 在一个实施例中，导电涂料从喷枪喷到电子模块或装置的外表面上。 固化喷涂的导电涂料以除去流体载体，留下金属膜涂覆在模块或装置的外部。 在与阵列形式的电子封装件一起使用的一个实施例中，沟槽被切割成模块的封装材料，使得屏蔽保护包括封装的侧壁。 在与相机模块一起使用的另一个实施例中，掩模用于选择性地屏蔽模块的部分。 在另一实施例中，屏蔽电连接到电子模块的电路的接地导体。

公开(公告)号：US20130248887A1

公开(公告)日：2013-09-26

申请号：US13845445

申请日：2013-03-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS PTE LTD

Inventor： Romain Coffy ,  Eric Saugier ,  Hk Looi ,  Norbert Chevrier

IPC: H01L31/0203 ,  H01L31/18

CPC classification number: H01L31/0203 ,  G01S7/481 ,  G01S17/026 ,  H01L25/167 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/181 ,  H03K17/941 ,  H03K2017/9455 ,  H03K2217/94026 ,  H03K2217/94112 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.

Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。

公开(公告)号：US08535980B2

公开(公告)日：2013-09-17

申请号：US12977697

申请日：2010-12-23

Applicant: Puay Gek Chua ,  Yonggang Jin

Inventor： Puay Gek Chua ,  Yonggang Jin

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T408/566 ,  H01L2924/014 ,  H01L2924/00

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract translation: 提供了一种用于制造半导体封装的工艺，其包括在重构的晶片中钻孔盲孔，将覆盖在晶片上的干膜抗蚀剂粘附在孔上，以及图案化膜以暴露每个孔周围的空间。 然后通过在胶片的表面上擦拭一定量的糊料，将导电浆料填充到孔和空间中，使得糊料被迫进入空间和孔。 孔周围的空间限定了其厚度受薄膜厚度限制的接触垫，优选为约10μm或更小。 为了防止糊料在孔中捕获气穴，擦拭过程可以在空气中进行大量或全部空气的​​室中进行。 在固化糊料之后，晶片从后面变薄以露出孔中的固化糊料。

公开(公告)号：US08502394B2

公开(公告)日：2013-08-06

申请号：US12651080

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.

Abstract translation: 多堆叠半导体晶片组件在普通封装脚印上增强了板级可靠性和集成电气功能。 多层半导体晶片组件包括具有阶梯状上表面的底模。 台阶状上表面包括基部区域和相对于基底区域升高的阶梯状区域。 基部区域包括多个附接结构，其尺寸和形状被容纳以接纳导电球。 上模具堆叠在底模上方。 上模具包括多个附接结构，其尺寸和形状适于容纳导电球，并且被布置成与底模的附接结构对准。 导电球连接到底模的附接结构和上模的附接结构。