公开(公告)号：US06427323B2

公开(公告)日：2002-08-06

申请号：US09859690

申请日：2001-05-17

申请人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

发明人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

IPC分类号： H05K336

CPC分类号： H05K3/325 ,  H05K3/4614 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/10666 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49194

摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”

摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。

公开(公告)号：US06393696B1

公开(公告)日：2002-05-28

申请号：US09469795

申请日：1999-12-21

申请人： Kyung-Ro Yoon ,  Keon-Yang Park ,  Byung-Kook Sun

发明人： Kyung-Ro Yoon ,  Keon-Yang Park ,  Byung-Kook Sun

IPC分类号： H05K336

CPC分类号： H01L23/49833 ,  H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09845 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2924/00014

摘要： A method for manufacturing a printed circuit board is disclosed. When a metal is plated on an upper board to form a circuit, bonding fingers for being bonded with a semiconductor chip are prevented from being electroplated with a metal. That is, a slot with an ink layer formed therein is formed in each of a plurality of boards. Then window regions of different sizes are defined, and a working is carried out on the portion where the slots are not formed. That is, the copper clad laminates are subjected to a working to form slots, and an ink layer is formed within each of the slots. In this manner, during the plating of the upper face of the printed circuit board, the metal is prevented from intruding into the window region, thereby preventing the formation of a short circuit.

摘要翻译： 公开了一种印刷电路板的制造方法。 当金属镀在上板上以形成电路时，防止与半导体芯片接合的接合指状物被金属电镀。 也就是说，在多个板中的每一个中形成有形成有油墨层的槽。 然后定义不同尺寸的窗口区域，并且在未形成槽的部分进行加工。 也就是说，覆铜层压板经受加工以形成槽，并且在每个槽内形成油墨层。 以这种方式，在印刷电路板的上表面的电镀期间，防止金属进入窗口区域，从而防止形成短路。

公开(公告)号：US06370748B1

公开(公告)日：2002-04-16

申请号：US09538447

申请日：2000-03-30

申请人： Gisulfo Baccini

发明人： Gisulfo Baccini

IPC分类号： H05K336

CPC分类号： H05K3/4638 ,  H05K1/0306 ,  H05K3/00 ,  H05K3/1216 ,  H05K3/4629 ,  H05K2203/065 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/5193

摘要： Device to produce multi-layer electronic circuits each consisting of a plurality of individual circuits each made on a base support (12) on which electrically conductive material is deposited able to embody determined conductor tracks, said device comprising at least a printing station (13) able to deposit said electrically conductive material onto said base support (12) and a drying and cooling station (14), downstream of said drying and cooling station (14) there being provided an assembly station (16) able to superimpose a plurality of base supports (12) one on top of the other, on which base supports (12) individual electronic circuits are made, selectively alternating with electrically insulating sheets (92).

摘要翻译： 用于制造多层电子电路的装置，每个多层电子电路由多个独立电路构成，每个电路各自在其上沉积有导电材料的基底支撑件（12）上，其能够体现确定的导体轨迹，所述装置至少包括印刷站（13） 能够将所述导电材料沉积到所述基座支撑件（12）上，并且在所述干燥和冷却站（14）的下游设有干燥和冷却站（14），所述干燥和冷却站（14）设置有能够叠加多个基座 支撑件（12）一个在另一个之上，在其上形成有单个电子电路的基座支撑件（12），与电绝缘片（92）选择性地交替。

公开(公告)号：US06341417B1

公开(公告)日：2002-01-29

申请号：US09404510

申请日：1999-09-23

申请人： Dinesh Gupta ,  Lester Wynn Herron ,  John U. Knickerbocker ,  David C. Long ,  Jawahar P. Nayak ,  Keith C. O'Neil ,  Brenda L. Peterson

发明人： Dinesh Gupta ,  Lester Wynn Herron ,  John U. Knickerbocker ,  David C. Long ,  Jawahar P. Nayak ,  Keith C. O'Neil ,  Brenda L. Peterson

IPC分类号： H05K336

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0298 ,  H05K1/0306 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.

摘要翻译： 用于个性化多层衬底结构的方法和结构包括提供具有电特征并改变电特征的通用层以产生多层衬底的个性化层。

公开(公告)号：US06338194B1

公开(公告)日：2002-01-15

申请号：US09477003

申请日：2000-01-03

申请人： Gerhard Benz ,  Jürgen Finze ,  Manfred Walker

发明人： Gerhard Benz ,  Jürgen Finze ,  Manfred Walker

IPC分类号： H05K336

CPC分类号： H05K13/0069 ,  H05K3/0097 ,  H05K2203/0165 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49144

摘要： A method of making an assembly comprised of several circuitized substrates, e.g., printed circuit boards, frictionally retained within a common carrier through the use of appropriate, paired locking means. The method is adapted for subsequent processing (e.g., electronic component attach) of the substrates while assuring substrate retention. Subsequently, the substrates can be readily separated (removed) from the carrier.

摘要翻译： 通过使用合适的配对锁定装置，将由几个电路化基板（例如印刷电路板）构成的组件摩擦地保持在公共载体内。 该方法适用于随后处理（例如，电子部件附着）基板，同时确保基板保持。 随后，可以容易地将基底与载体分离（除去）。

公开(公告)号：US06308405B1

公开(公告)日：2001-10-30

申请号：US08967784

申请日：1997-11-10

申请人： Osamu Takamatsu ,  Katsunori Hatanaka ,  Kiyoshi Takimoto ,  Haruki Kawada ,  Ken Eguchi ,  Yuko Morikawa ,  Hiroshi Matsuda ,  Toshihiko Takeda ,  Yoshihiro Yanagisawa ,  Hisaaki Kawade ,  Hideyuki Kawagishi

发明人： Osamu Takamatsu ,  Katsunori Hatanaka ,  Kiyoshi Takimoto ,  Haruki Kawada ,  Ken Eguchi ,  Yuko Morikawa ,  Hiroshi Matsuda ,  Toshihiko Takeda ,  Yoshihiro Yanagisawa ,  Hisaaki Kawade ,  Hideyuki Kawagishi

IPC分类号： H05K336

CPC分类号： B05D1/202 ,  B82Y30/00 ,  B82Y40/00 ,  G11B9/00 ,  G11B11/08 ,  Y10T29/49032 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

摘要： An electrode substrate and a recording medium having a smooth surface with surface unevenness of 1 nm or less and a size of 1 &mgr;m□ or more are disclosed. An electrode substrate and a recording medium having a concave-shaped groove for tracking on the surface, which groove has a depth which can detect of the tunnel current from the bottom thereof by a probe electrode for scanning the surface are also disclosed. Information processing devices equipped with the smooth recording medium, an electroconductive probe arranged approximate to the recording medium and a pulse voltage application circuit for recording are also disclosed.

摘要翻译： 公开了具有1nm以下的表面凹凸的平滑表面和1mum以上的尺寸的电极基板和记录介质。 还公开了一种具有用于在表面上跟踪的凹形槽的电极基板和记录介质，该凹槽具有可以通过用于扫描该表面的探针电极从其底部检测隧道电流的深度。 还公开了配备有平滑记录介质的信息处理设备，近似于记录介质的导电探针和用于记录的脉冲电压施加电路。

公开(公告)号：US06230397B1

公开(公告)日：2001-05-15

申请号：US09281423

申请日：1999-03-30

申请人： Thomas S. Tighe

发明人： Thomas S. Tighe

IPC分类号： H05K336

CPC分类号： H01R12/62 ,  H01R12/772 ,  H05K3/365 ,  H05K3/4092 ,  Y10T29/49126 ,  Y10T29/49149 ,  Y10T29/49213

摘要： A new electrical cryogenic connector system employs two printed circuit board type mating connectors (1 & 3), each containing a plurality of plated-on metal lines (5 & 6) running along the respective circuit boards in parallel, with the plated-on onmetal lines on at least one of the connectors being of Beryllium Copper material. The ends of the series of Beryllium Copper lines on one of the complementary circuit boards is formed into a pointed spring finger that is pointed toward the opposed circuit board. With the two boards sandwiched and pressed together with their plated on metal lines directly in line with and facing one another, the spring fingers compress and, under the spring force created by that compression, the spring fingers engage and maintain positive electrical contact with the corresponding conductor traces on the opposed circuit board. Ancillary to the described connector, a new method for constructing an electrical connector is also presented.

摘要翻译： 一种新的低温电连接器系统采用两个印刷电路板型配合连接器（1和3），每个连接器包含沿着各个电路板平行延伸的多个电镀金属线（5和6），镀上金属 至少一个连接器上的线是铍铜材料。 在其中一个互补电路板上的一系列铍铜线的端部形成为指向相对的电路板的尖锐的弹簧手指。 将两个板夹在一起并与金属线对齐，直接与金属线对齐并相互面对，弹簧指压缩，并且在由该压缩产生的弹簧力的作用下，弹簧指接合并保持与相应的弹性指向的正电接触 相对电路板上的导体迹线。 附带说明的连接器，还提出了一种用于构建电连接器的新方法。

公开(公告)号：US06708399B2

公开(公告)日：2004-03-23

申请号：US09834805

申请日：2001-04-12

申请人： Warren M. Farnworth ,  Salman Akram

发明人： Warren M. Farnworth ,  Salman Akram

IPC分类号： H05K336

CPC分类号： G01R1/0466 ,  G01R1/06738 ,  G01R1/07314 ,  G01R1/07378 ,  G01R3/00 ,  H05K3/326 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method for fabricating an interconnect for testing semiconductor components forms contacts on a substrate configured to support and electrically engage bumped contacts on the components. Each contact includes a support member suspended on the substrate on cantilevered spring segment leads. The method includes the steps of forming a polymer material on the substrate, forming a metal layer on the polymer material and the substrate, forming the support member and leads in the metal layer, and then removing the polymer material to suspend the support member. In a first embodiment the polymer material fills a recess in the substrate and the support member is suspended on the recess. In a second embodiment the polymer material is formed as a bump, and the support member is suspended on a surface of the substrate.

摘要翻译： 用于制造用于测试半导体部件的互连的方法在被配置为支撑和电接合部件上的凸起接触的基板上形成接触。 每个触点包括在悬臂弹簧段导线上悬挂在基板上的支撑构件。 该方法包括以下步骤：在基底上形成聚合物材料，在聚合物材料和基底上形成金属层，在金属层中形成支撑构件和引线，然后除去聚合物材料以悬浮支撑构件。 在第一实施例中，聚合物材料填充衬底中的凹部，并且支撑构件悬挂在凹部上。 在第二实施例中，聚合物材料形成为凸块，并且支撑构件悬挂在基板的表面上。

公开(公告)号：US06687985B2

公开(公告)日：2004-02-10

申请号：US09902771

申请日：2001-07-12

申请人： Kazunori Sakamoto ,  Hideo Hatanaka ,  Yukihiro Ishimaru ,  Tosaku Nishiyama

发明人： Kazunori Sakamoto ,  Hideo Hatanaka ,  Yukihiro Ishimaru ,  Tosaku Nishiyama

IPC分类号： H05K336

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/49 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/142 ,  H05K3/4697 ,  H05K2201/048 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multilayer wiring board comprising a mother wiring board and a carrier wiring board, in which all of the composing layers have IVH structure. The mother wiring board (11) is formed in the manner that a plurality of resin-impregnated-fiber-sheets having mother wiring layers (13) and first inner-via-hole conductors (14) for connecting the wiring layers (13) each other are laminated. The mother wiring board (11) comprises a base board (11a) and container board (11b) having an opening for forming a cavity (15). The carrier wiring board (16) has lands (17) for mounting LSI bare chips, wirings (18), a plurality of carrier-board-wiring-layers (19) and second inner-via-hole conductors (20) for connecting the wiring layers (19) each other. The carrier wiring board (16) is set in the cavity (15) for electrically connecting the carrier wiring board (16) to the mother wiring board (11) by connecting carrier board electrodes (21) to mother board electrodes (22) through connectors (23) of solder balls, gold bumps or electrically conductive paste. The carrier wiring board (16) has higher wiring density at the portion where LSI bare chips are mounted, than the mother wiring board.

摘要翻译： 一种多层布线板，包括母布线板和载体布线板，其中所有构成层均具有IVH结构。 母布线板（11）形成为具有母布线层（13）的多个树脂浸渍纤维片和用于将布线层（13）各自连接的第一内通孔导体（14） 其他的是层压的。 母接线板（11）包括具有用于形成空腔（15）的开口的基板（11a）和容器板（11b）。 载体布线板（16）具有用于安装LSI裸芯片的布线板（17），布线（18），多个载板布线层（19）和第二内通孔导体（20），用于将 布线层（19）。 载体布线板（16）设置在通过连接器（15）将载体布线板（16）与母线路板（11）电连接到母板电极（22）的腔（15）中， （23）焊球，金凸块或导电膏。 载体布线板（16）在LSI裸芯片的安装部分的布线密度比母布线板高。

公开(公告)号：US06684493B2

公开(公告)日：2004-02-03

申请号：US10099483

申请日：2002-03-13

申请人： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

发明人： Larry D. Kinsman ,  Walter L. Moden ,  Warren M. Farnworth

IPC分类号： H05K336

CPC分类号： H05K3/301 ,  H01L23/32 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

摘要： A support assembly for mounting a semiconductor device vertically relative to a carrier substrate is disclosed. The support assembly includes an interposer to which the semiconductor device is attached. The support assembly also includes traces carried on the interposer, which electronically connect the semiconductor device to contacts on the interposer. The contacts are disposed along a single edge of the interposer. The invention also includes an alignment device for releaseably mounting the support assembly. The alignment device, which mounts to a carrier substrate, includes one or more receptacles. As a support assembly is inserted into a receptacle, the alignment device establishes an electrical connection between the contacts and corresponding terminals on the carrier substrate. The assembly may also include a cover that attaches to the top of the alignment device and biases the interposer against the carrier substrate.

摘要翻译： 公开了一种用于相对于载体衬底垂直安装半导体器件的支撑组件。 支撑组件包括插入件，半导体器件附接到该插入器。 支撑组件还包括承载在插入器上的迹线，其将半导体器件电连接到插入器上的触点。 触点沿着插入器的单个边缘设置。 本发明还包括用于可释放地安装支撑组件的对准装置。 安装到载体基板的对准装置包括一个或多个插座。 当支撑组件插入到插座中时，对准装置在触点和载体基板上的相应端子之间建立电连接。 组件还可以包括附接到对准装置的顶部并将插入件偏压抵靠载体基板的盖。