公开(公告)号：US20180102387A1

公开(公告)日：2018-04-12

申请号：US15839292

申请日：2017-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Axel Crocherie ,  Jean-Pierre Oddou ,  Stéphane Allegret-Maret ,  Hugues Leininger

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

公开(公告)号：US09941416B2

公开(公告)日：2018-04-10

申请号：US15356022

申请日：2016-11-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L31/119 ,  H01L29/786 ,  H01L21/762 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

公开(公告)号：US20180083060A1

公开(公告)日：2018-03-22

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US09922871B2

公开(公告)日：2018-03-20

申请号：US15401896

申请日：2017-01-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Petitprez

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/0217 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76835 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/84 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/518 ,  H01L29/7838

Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.

公开(公告)号：US09911827B2

公开(公告)日：2018-03-06

申请号：US15372930

申请日：2016-12-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Louis Hutin ,  Julien Borrel ,  Yves Morand ,  Fabrice Nemouchi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

公开(公告)号：US20180061955A1

公开(公告)日：2018-03-01

申请号：US15467082

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853

Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.

公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US09891450B2

公开(公告)日：2018-02-13

申请号：US15084645

申请日：2016-03-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles Baudot ,  Maurin Douix ,  Frédéric Boeuf ,  Sébastien Cremer

IPC: G02F1/035 ,  G02F1/025 ,  G02F1/015

CPC classification number: G02F1/025 ,  G02F2001/0151

Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.

公开(公告)号：US20180038907A1

公开(公告)日：2018-02-08

申请号：US15468798

申请日：2017-03-24

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Chittoor Parthasarathy

IPC: G01R31/28

CPC classification number: G01R31/2858 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/2896

Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.

公开(公告)号：US20180006072A1

公开(公告)日：2018-01-04

申请号：US15198824

申请日：2016-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Bastien Mamdy

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464

Abstract: A photosensor is formed within a semiconductor substrate layer having a front side and a back side. An isolation structure delimits an active region of the semiconductor substrate layer which includes a charge collecting region. The front side of semiconductor substrate layer includes a charge transfer circuit. A reflecting mirror is mounted at the back side of the semiconductor substrate layer. The reflecting mirror includes a pupil opening configured to admit light into the active region at the back side. An underside reflective surface of the reflecting mirror is configured to reflect light received from the active region back into the active region.