公开(公告)号：US12048123B2

公开(公告)日：2024-07-23

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

CPC classification number: H05K7/205

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US12047357B2

公开(公告)日：2024-07-23

申请号：US17556671

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Cesar Martinez-Spessot ,  Marcos Carranza ,  Lakshmi Talluru ,  Mateo Guzman ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rajesh Poornachandran ,  Kshitij Arun Doshi

IPC: H04L9/40 ,  G06F9/54

CPC classification number: H04L63/0428 ,  G06F9/547

Abstract: Embodiments described herein are generally directed to a transparent and adaptable mechanism for performing secure application communications through sidecars. In an example, a set of security features is discovered by a first sidecar of a first microservice of multiple microservices of an application. The set of security features are associated with a device of multiple devices of a set of one or more host systems on which the first microservice is running. Information regarding the set of discovered security features is made available to the other microservices by the first sidecar by sharing the information with a discovery service accessible to all of the microservices. A configuration of a communication channel through which a message is to be transmitted from a second microservice to the first microservice is determined by a second sidecar of the second microservice by issuing a request to the discovery service regarding the first microservice.

公开(公告)号：US12046819B2

公开(公告)日：2024-07-23

申请号：US17448724

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Maruti Tamrakar ,  Sagar Gupta ,  Jayprakash Thakur ,  Prasanna Pichumani

IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q13/10 ,  H01Q21/06

CPC classification number: H01Q21/064 ,  H01Q1/38 ,  H01Q13/106

Abstract: A slot antenna assembly for a portable electronic device is disclosed. The assembly includes a first slot antenna having a first slot through a substrate from an outer surface of the substrate to an inner surface of the substrate. The assembly also includes a second slot antenna including a second slot through the substrate from the outer surface of the substrate to the inner surface of the substrate. An isolator includes at least one of an isolation slot and a conductor. The isolation slot includes a substrate isolation slot which extends through the substrate between the first and second slot antennas; and a conductor. The conductor connects the inner surface of the substrate between the first and second antennas to an opposite inner surface of an opposite substrate opposite the inner surface between the first and second antennas.

公开(公告)号：US12046654B2

公开(公告)日：2024-07-23

申请号：US16912118

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Dan S. Lavric ,  Glenn A. Glass ,  Thomas T. Troeger ,  Suresh Vishwanath ,  Jitendra Kumar Jha ,  John F. Richards ,  Anand S. Murthy ,  Srijit Mukherjee

IPC: H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US12046600B2

公开(公告)日：2024-07-23

申请号：US18088463

申请日：2022-12-23

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

公开(公告)号：US12046568B2

公开(公告)日：2024-07-23

申请号：US18214742

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L23/48

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5389 ,  H01L25/16 ,  H01L25/50 ,  H01L23/481 ,  H01L2223/6666 ,  H01L2223/6672

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US12045466B2

公开(公告)日：2024-07-23

申请号：US16861551

申请日：2020-04-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat

IPC: G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0611 ,  G06F3/0637 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4881

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a current access request for a storage media associated with a stream, identify a hint in the current access request which indicates one or more stream characteristics for future access requests from the stream, and handle the current access request based on the indicated one or more stream characteristics for future access requests from the stream. Other embodiments are disclosed and claimed.

公开(公告)号：US12042259B2

公开(公告)日：2024-07-23

申请号：US17735749

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Indira Negi

IPC: A61B5/024 ,  A61B5/00 ,  A61B5/11

CPC classification number: A61B5/02438 ,  A61B5/6803 ,  A61B5/1102

Abstract: An apparatus for sensing a heart rate of a subject, including an eyewear frame and a heart rate sensing circuit. The sensing circuit includes first and second piezoelectric sensors configured to be in communication with the subject's skin and to generate first and second voltage signals in response to a periodic vibration in at least one artery of the subject, a first voltage amplifier configured to receive the first voltage signal and output a first amplified voltage signal related to the heart rate of the subject, a second voltage amplifier configured to receive the second voltage signal and output a second amplified voltage signal related to the heart rate of the subject, and a device configured to output a differential signal that is a representation of a difference between the first amplified voltage signal and the second amplified voltage signal that relates to the heart rate.

公开(公告)号：US20240244772A1

公开(公告)日：2024-07-18

申请号：US18619554

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Smit Kapila ,  Jeff Ku ,  Min Suet Lim ,  Sarma Vmk Vedhanabhatla

IPC: H05K5/02

CPC classification number: H05K5/0213

Abstract: Techniques are described to dynamically adjust the open air ratio (OAR) while ensuring compliance with regulatory requirements. An adjustable thermal vent assembly is described that dynamically adjusts the OAR for inlet/outlet vents depending on the current use case. The adjustable thermal vent assembly functions to increase the grating spacing only when a triggering condition is met that ensures that a corresponding thermal vent location is inaccessible. Such temporarily inaccessible regions may include the bottom cover of an electronic device when positioned on the surface of an object, for thermal intake vents, or the rear portion of an electronic device when the display cover exceeds a predetermined angle, for thermal exhaust vents.

公开(公告)号：US20240243088A1

公开(公告)日：2024-07-18

申请号：US18622486

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

CPC classification number: H01L24/14 ,  C25D3/38 ,  C25D5/022 ,  C25D7/12 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/1403

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.