Patent search ap:"MONOLITHIC 3D INC." Page 63

621.

发明申请
SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

公开(公告)号：US20190312014A1

公开(公告)日：2019-10-10

申请号：US16450728

申请日：2019-06-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L25/07 , H01L23/544

Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.

622.

发明申请
3D SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20190237461A1

公开(公告)日：2019-08-01

申请号：US16242300

申请日：2019-01-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Zeev Wurman

IPC: H01L27/06 , H01L29/812 , H01L29/808 , H01L27/092 , H01L29/732 , H01L29/66 , H01L21/8238 , H01L21/768 , H01L29/786 , H01L29/45 , H01L29/423 , H01L23/367 , H01L27/12 , H01L27/118 , H01L27/11578 , H01L27/11551 , H01L27/112 , H01L27/11 , H01L27/108 , H01L27/105 , H01L27/02 , H01L23/544 , H01L23/48 , H01L21/84 , H01L21/822 , H01L21/762 , G03F9/00 , H01L23/532 , H01L23/528 , H01L23/522

CPC classification number: H01L27/0688 , G03F9/7076 , G03F9/7084 , H01L21/268 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823871 , H01L21/84 , H01L23/367 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/73 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/42392 , H01L29/458 , H01L29/66272 , H01L29/66545 , H01L29/66621 , H01L29/66848 , H01L29/66901 , H01L29/732 , H01L29/78639 , H01L29/78642 , H01L29/78645 , H01L29/808 , H01L29/812 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025

Abstract: A 3D semiconductor device including: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.

623.

发明授权
3D semiconductor device and structure 有权

公开(公告)号：US10366970B2

公开(公告)日：2019-07-30

申请号：US16024911

申请日：2018-07-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar , Zvi Or-Bach , Brian Cronquist

IPC: H01L21/00 , H01L25/065 , H01L23/48 , H01L27/06 , H01L27/088 , H01L23/522 , H01L23/367 , H01L21/822 , H01L27/092 , H01L21/8234

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

624.

发明申请
3D SEMICONDUCTOR DEVICE AND SYSTEM 审中-公开

公开(公告)号：US20190139827A1

公开(公告)日：2019-05-09

申请号：US16166598

申请日：2018-10-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist

IPC: H01L21/822 , H01L21/8238 , G11C17/14 , H01L21/683 , H01L29/786 , H01L29/78 , H01L21/84 , G11C29/00 , G11C17/06 , G11C16/04 , H03K19/177 , H03K19/0948 , H03K17/687 , H01L27/118 , H01L27/112 , H01L27/11 , H01L27/108 , H01L27/105 , H01L27/092 , H01L27/06 , H01L27/02 , H01L25/18 , H01L21/762 , H01L25/065 , H01L23/544 , H01L23/525 , H01L23/36

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where the contact plugs are connected to the plurality of first single crystal transistors and the first metal layer, where the first metal layer interconnect the first single crystal transistors forming memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a second metal layer; a third metal layer, where the second metal layer overlays the third level, where the third metal layer overlays the second metal layer, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, where the memory control circuits include control sub-circuits to remap a degraded memory block to an alternative memory space within the device.

625.

发明申请
3D SEMICONDUCTOR DEVICE AND SYSTEM 审中-公开

公开(公告)号：US20190109049A1

公开(公告)日：2019-04-11

申请号：US16180172

申请日：2018-11-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist

IPC: H01L21/822 , H01L21/8238 , H01L25/065 , H01L21/84 , H01L23/36 , H01L23/525 , H01L23/544 , H01L21/762 , H01L25/18 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/118 , H03K17/687 , H03K19/0948 , H03K19/177 , G11C16/04 , G11C17/06 , G11C29/00 , H01L29/78 , H01L29/786 , H01L21/683 , G11C17/14 , H01L23/00 , H01L23/48

Abstract: A 3D semiconductor device including: a first level comprising first single crystal transistors, a first metal layer, and a plurality of latches; a second level comprising a plurality of second transistors, wherein said second level comprises first memory cells, and wherein said first memory cells each comprise at least one of said plurality of second transistors; a third level comprising a plurality of third transistors, wherein said third level comprises second memory cells, wherein said second memory cells each comprise at least one of said plurality of third transistors, wherein said second level overlays said first level, and wherein said third level overlays said second level; a second metal layer overlaying said third level, said second metal layer comprising a plurality of bit-lines, wherein said plurality of second transistors are aligned to said first single crystal transistors with less than 100 nm alignment error, wherein said plurality of second transistors are junction-less transistors, and wherein each of said plurality of bit lines is connected to at least one of said plurality of latches.

626.

发明申请
3D SEMICONDUCTOR DEVICE AND SYSTEM 审中-公开

公开(公告)号：US20190074222A1

公开(公告)日：2019-03-07

申请号：US16179914

申请日：2018-11-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist

IPC: H01L21/822 , H03K19/177 , H03K19/0948 , H03K17/687 , H01L29/786 , H01L29/78 , H01L27/118 , H01L27/112 , H01L27/11 , H01L27/108 , H01L27/105 , H01L27/092 , H01L27/06 , H01L27/02 , H01L25/18 , H01L25/065 , H01L23/544 , H01L23/525 , H01L23/36 , H01L21/84 , H01L21/8238 , H01L21/762 , H01L21/683 , G11C29/00 , G11C17/14 , G11C17/06 , G11C16/04 , H01L23/48 , H01L23/00

Abstract: A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of second transistors; where the second level includes memory cells including the plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level; and vertically oriented conductive plugs, the vertically oriented conductive plugs connect from the second transistors to the first metal layer, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, and where one end of at least one of the vertically oriented conductive plugs functions also as a contact to a portion of each of the plurality of second transistors.

627.

发明申请
MULTI-LEVEL SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE 审中-公开

公开(公告)号：US20180350823A1

公开(公告)日：2018-12-06

申请号：US15990611

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach , Jin-Woo Han

IPC: H01L27/112 , H01L27/11556 , H01L27/11582 , H01L27/11529 , H01L27/11573 , H01L23/48

CPC classification number: H01L27/11286 , G11C5/025 , G11C13/0023 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C17/165 , G11C2213/71 , H01L23/481 , H01L27/10802 , H01L27/1104 , H01L27/11519 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/24

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.