公开(公告)号：US20180331073A1

公开(公告)日：2018-11-15

申请号：US16024911

申请日：2018-07-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

公开(公告)号：US10038073B1

公开(公告)日：2018-07-31

申请号：US15917629

申请日：2018-03-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00 ,  H01L29/66 ,  H01L23/50 ,  H01L23/34 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L27/108 ,  H01L23/544 ,  H01L21/74 ,  H01L29/10 ,  H01L29/808 ,  H01L29/732 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11526 ,  H01L23/48 ,  H01L27/06 ,  H01L27/24

Abstract: A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.

公开(公告)号：US20180204930A1

公开(公告)日：2018-07-19

申请号：US15917629

申请日：2018-03-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/66 ,  H01L23/50 ,  H01L23/48 ,  H01L23/34 ,  H01L27/088

CPC classification number: H01L29/66704 ,  H01L21/743 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L45/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152

Abstract: A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.

公开(公告)号：US20180204826A1

公开(公告)日：2018-07-19

申请号：US15920499

申请日：2018-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L25/16 ,  H01L21/762 ,  H01L23/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L33/38

Abstract: A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.

公开(公告)号：US20180190811A1

公开(公告)日：2018-07-05

申请号：US15862616

申请日：2018-01-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/78

CPC classification number: H01L27/06 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/24 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78696

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

公开(公告)号：US20180190619A1

公开(公告)日：2018-07-05

申请号：US15904377

申请日：2018-02-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

公开(公告)号：US10014318B2

公开(公告)日：2018-07-03

申请号：US15333138

申请日：2016-10-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/11514

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.

公开(公告)号：US10014282B2

公开(公告)日：2018-07-03

申请号：US15721955

申请日：2017-10-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/74 ,  H01L29/66 ,  H01L27/06 ,  H01L23/485 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092

Abstract: An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.

公开(公告)号：US10002865B2

公开(公告)日：2018-06-19

申请号：US15482761

申请日：2017-04-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H03K19/096 ,  H01L23/34 ,  H01L23/50 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L27/0688 ,  G11C11/401 ,  G11C29/006 ,  G11C29/76 ,  H01L22/22 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5252 ,  H01L23/5286 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099

Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.

公开(公告)号：US09953994B2

公开(公告)日：2018-04-24

申请号：US15344562

申请日：2016-11-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/11565 ,  H01L29/792 ,  G11C16/04 ,  G11C14/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L29/78 ,  G11C11/56

CPC classification number: H01L27/11568 ,  G11C11/5621 ,  G11C14/0018 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L27/11565 ,  H01L28/00 ,  H01L29/7831 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.