公开(公告)号：US09911820B2

公开(公告)日：2018-03-06

申请号：US15464763

申请日：2017-03-21

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cyrille Le Royer ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US09911737B2

公开(公告)日：2018-03-06

申请号：US14435004

申请日：2013-10-11

Applicant: STMicroelectronics SA ,  Commissariat àl'énergie atomique et aux énergies alternatives

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Jean-Philippe Noel ,  Bertrand Pelloux-Prayer

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823892 ,  H01L27/1203

Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

公开(公告)号：US09853345B2

公开(公告)日：2017-12-26

申请号：US14986315

申请日：2015-12-31

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frédéric Gianesello

IPC: H04B1/40 ,  H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/24 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  H03F3/20 ,  H03F3/19 ,  H03F3/21

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

公开(公告)号：US09847349B1

公开(公告)日：2017-12-19

申请号：US15463493

申请日：2017-03-20

Applicant: STMicroelectronics SA

Inventor： Augustin Monroy Aguirre ,  Guillaume Bertrand ,  Philippe Cathelin ,  Raphael Paulin

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/45 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/78615

Abstract: An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.

公开(公告)号：US20170294379A1

公开(公告)日：2017-10-12

申请号：US15093416

申请日：2016-04-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76877 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/0649

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US20170288781A1

公开(公告)日：2017-10-05

申请号：US15083616

申请日：2016-03-29

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Jean-Francois Carpentier ,  Patrick Lemaitre ,  Jean-Robert Manouvrier ,  Denis Pache ,  Stephane Le Tual

IPC: H04B10/516 ,  H04L25/49

CPC classification number: H04B10/541 ,  G02F1/0121 ,  G02F1/2257 ,  H04B10/505 ,  H04L25/4917

Abstract: An optical modulator includes an optical waveguide including at least a first PN junction phase shifter and a second PN junction phase shifter. A driver circuit drives operation of the first and second PN junction phase shifters in response to a pulse amplitude modulated (PAM) analog signal having 2n levels. The PAM analog signal is generated by a digital to analog converter that receives an n-bit input signal. In an implementation, the optical waveguide and PN junction phase shifters are formed on a first integrated circuit chip and the driver circuit is formed on a second integrated circuit chip that is stacked on and electrically connected to the first integrated circuit chip.

公开(公告)号：US09726548B2

公开(公告)日：2017-08-08

申请号：US14925753

申请日：2015-10-28

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreia Cathelin ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Janusz Grzyb ,  Yan Zhao

IPC: G01J5/22 ,  G01J5/10 ,  G01N21/3581 ,  G01J5/20 ,  H01Q23/00 ,  G01J5/00

CPC classification number: G01J5/22 ,  G01J5/10 ,  G01J5/20 ,  G01J2005/0077 ,  G01J2005/202 ,  G01N21/3581 ,  H01Q23/00 ,  Y10T29/49018

Abstract: A terahertz imager includes an array of pixel circuits. Each pixel circuit has an antenna and a detector. The detector is coupled to differential output terminals of the antenna. A frequency oscillator is configured to generate a frequency signal on an output line. The output line is coupled to an input terminal of the antenna of at least one of the pixel circuits.

公开(公告)号：US20170194498A1

公开(公告)日：2017-07-06

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US09685472B2

公开(公告)日：2017-06-20

申请号：US15050579

申请日：2016-02-23

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel Crocherie ,  Michel Marty ,  Jean-Luc Huguenin ,  Sébastien Jouan

IPC: H01L21/00 ,  H01L31/113 ,  H01L27/146 ,  H01L29/66

CPC classification number: H01L29/66977 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14685 ,  H01L2027/11892 ,  H04N2209/045

Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer above the photodiode, a dielectric region above the antireflection layer and an optical filter to pass incident luminous radiation having a given wavelength. The antireflection layer may include an array of pads mutually separated by a dielectric material of the dielectric region. The array may be configured to allow simultaneous transmission of the incident luminous radiation and a diffraction of the incident luminous radiation producing diffracted radiations which have wavelengths below that of the incident radiation, and are attenuated with respect to the incident radiation.

公开(公告)号：US09684631B2

公开(公告)日：2017-06-20

申请号：US14511843

申请日：2014-10-10

Applicant: STMicroelectronics SA

Inventor： Philippe Escalona

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/76 ,  G06F21/75 ,  G06F21/00

CPC classification number: G06F15/76 ,  G06F9/30156 ,  G06F21/00 ,  G06F21/75

Abstract: A method for securing a data processing system having a processing unit is disclosed. At least a group of N1 digital words of m1 bits is selected from among the set of M1 digital words. N1 is less than M1. These words are selected in such a way that each selected digital word differs from all the other selected digital words by a number of bits at least equal to an integer p which is at least equal to 2. The group of N1 digital words of m1 bits form at least one group of N1 executable digital instructions. The processing unit is configured to make it capable of executing each instruction of the at least one group of N1 executable digital instructions.