公开(公告)号：US12147982B1

公开(公告)日：2024-11-19

申请号：US18357773

申请日：2023-07-24

Applicant: United Services Automobile Association (USAA)

Inventor： Bharat Prasad ,  Ruthie D. Lyle ,  Minya Liang ,  Thomas Bret Buckingham

IPC: G06Q20/40 ,  G06F16/27 ,  G06Q20/06 ,  G06Q20/32

Abstract: Techniques are described for managing devices, such as Internet of Things (IoT) devices, using smart contract(s) on a distributed ledger (e.g., blockchain). Smart contract(s) executing on a distributed ledger may control access to one or more devices in a home or other environment. The smart contract(s) may employ information stored on the distributed ledger and information in a transaction sent to the smart contract(s) to determine whether particular user(s) and/or process(es) may access the device(s), issue commands to the device(s), access data generated by the device(s), and/or control the device(s). The smart contract(s) may provide a secure portal through which user(s) and/or service(s) may access device(s) for command and control of such device(s), and secure access may be based on permission information that is specified or provided by an owner or operator of the device(s) and that is stored on the distributed ledger.

公开(公告)号：US12142313B2

公开(公告)日：2024-11-12

申请号：US17591302

申请日：2022-02-02

Applicant: Lodestar Licensing Group, LLC

Inventor： Joo-Sang Lee ,  John E. Riley

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/409

Abstract: A memory device includes at least one memory bank comprising a set of redundant word lines, a set of normal word lines, and row hammer refresh logic. The RHR logic comprises a first input to receive a first signal indicative of whether a match was generated at a fuse of the memory device, a second input to receive a redundant row address corresponding to a first location of a memory array of the memory device, a third input to receive a word line address corresponding to a second location of the memory array of the memory device. The RHR logic also comprises an output to transmit at least one first memory address adjacent to the first location or at least one second memory address adjacent to the second location based on a value of the first signal.

公开(公告)号：US12142219B1

公开(公告)日：2024-11-12

申请号：US18465978

申请日：2023-09-12

Applicant: Apple Inc.

Inventor： Tae-Wook Koh ,  Mahesh B Chappalli ,  Jared S Price ,  Vincent Z Young ,  Yifan Zhang

IPC: G09G5/10 ,  G09G3/3233

Abstract: An electronic device may include an electronic display having a pixel and that displays an image based on compensated image data. The electronic device may also include image processing circuitry communicatively coupled to the electronic display. The image processing circuitry may receive image data and determine a gain value for the pixel based on an aging value of the pixel that is based on previously displayed pixel values of the pixel. The image processing circuitry may also adjust the gain value based on a pixel value of the image data corresponding to the pixel to generate an updated gain value and adjust the pixel value of the image data based on the updated gain value to generate, at least in part, the compensated image data.

公开(公告)号：US12142118B1

公开(公告)日：2024-11-12

申请号：US18220111

申请日：2023-07-10

Applicant: United Services Automobile Association (USAA)

Inventor： Ashley Raine Philbrick ,  Oscar Guerra ,  Kelly Q. Baker ,  Carlos JP Chavez ,  Yevgeniy Viatcheslavovich Khmelev ,  Theresa Marie Matowitz

IPC: G07F19/00

Abstract: A method may include receiving, via a processor, a request for payment of a payment amount from a first computing system. The method may also involve receiving a location of the first computing system, identifying one or more automatic teller machines (ATMs) based on the location of the first computing system, generating an image configured to cause the one or more ATMs to dispense funds that correspond to the payment amount, and sending the image to the first computing system.

公开(公告)号：US12141304B1

公开(公告)日：2024-11-12

申请号：US18487736

申请日：2023-10-16

Applicant: UNITED SERVICES AUTOMOBILE ASSOCIATION (USAA)

Inventor： Gopinath Rangan ,  John C. Hopkins, III

IPC: G06F21/62

Abstract: Aspects herein relate to storing information concerning rights and liabilities or other records on distributed ledgers. A method disclosed can include identifying a transferor blockchain associated with rights and liabilities for transfer from a transferor to an acquirer, identifying an acquirer blockchain associated with the acquirer, creating an interim blockchain including the rights and liabilities, generating entries to the transferor blockchain removing the rights and liabilities, and generating entries to the acquirer blockchain adding the rights and liabilities. Another method disclosed can include identifying a critical record of a party, identifying a blockchain associated with the party, and generating an entry on the blockchain associated with the critical record, the entry having permissions related to at least the party.

公开(公告)号：US12135667B2

公开(公告)日：2024-11-05

申请号：US18327043

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L23/498 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US12135660B2

公开(公告)日：2024-11-05

申请号：US17701511

申请日：2022-03-22

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: H01L23/538 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C7/22 ,  G11C8/00 ,  G11C29/12 ,  H01L25/18 ,  H03K19/003 ,  H03K19/173 ,  H03K19/1776 ,  G06F1/00 ,  H01L23/00 ,  H01L25/065 ,  H03K19/00

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US12132451B2

公开(公告)日：2024-10-29

申请号：US17583018

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: H03F1/30 ,  G11C11/4074 ,  H02M3/155 ,  H03F1/02 ,  H03F3/21

CPC classification number: H03F1/301 ,  G11C11/4074 ,  H02M3/155 ,  H03F1/0233 ,  H03F3/211 ,  H03F2200/504

Abstract: Systems and devices are provided for tracking bandgap current generated by a bandgap circuit and mitigation of leakage current regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus and comprising a transistor. The apparatus may also include bandgap current mirroring circuitry that generates a mirrored current that mirrors a received current that is process, voltage, and temperature (PVT) independent. The apparatus may also include a bulk voltage generator circuit including an amplifier having an input coupled to the bandgap current mirroring circuitry. Bulk voltage control circuitry is coupled to an output of the amplifier and generates a bulk voltage based on the relationship between the mirrored current and the leakage current.

公开(公告)号：US12131712B2

公开(公告)日：2024-10-29

申请号：US17980252

申请日：2022-11-03

Applicant: Apple Inc.

Inventor： Vehbi Calayir ,  Youchul Jeong ,  Joshua D. Goldman

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0626 ,  G09G2360/145

Abstract: Large sized electronic displays may include a backlight that generates light to illuminate a display panel. The backlight is divided into tiles that each includes a set of backlight elements that are driven by respective tile driver circuitry. Based on receiving brightness data and/or control signals from a backlight controller (BCON) of the backlight, the respective tile driver circuitry drives corresponding backlight elements such that the backlight elements suitably illuminate the display panel.

公开(公告)号：US12130774B2

公开(公告)日：2024-10-29

申请号：US18103957

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: G06F15/78 ,  G06F1/3225 ,  G06F9/448 ,  G06F13/42 ,  G06N20/00 ,  G05B19/045 ,  G06F3/06

CPC classification number: G06F15/7867 ,  G06F1/3225 ,  G06F9/4498 ,  G06F13/423 ,  G06F15/7857 ,  G06N20/00 ,  G05B19/045 ,  G06F3/0604

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.