公开(公告)号：US20240164092A1

公开(公告)日：2024-05-16

申请号：US18389988

申请日：2023-12-20

Applicant: Lodestar Licensing Group, LLC

Inventor： Collin Howder ,  Chet E. Carter

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240161830A1

公开(公告)日：2024-05-16

申请号：US18225574

申请日：2023-07-24

Applicant: Lodestar Licensing Group, LLC

Inventor： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

IPC: G11C16/10 ,  G06F17/16 ,  G11C5/02 ,  G11C7/10 ,  G11C8/14 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G06F17/16 ,  G11C5/02 ,  G11C7/1039 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08

Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

公开(公告)号：US11977770B2

公开(公告)日：2024-05-07

申请号：US16029253

申请日：2018-07-06

Applicant: Lodestar Licensing Group LLC

Inventor： Frank F. Ross

IPC: G06F3/06 ,  G11C11/4093

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0673 ,  G11C11/4093

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating the need for repeated polling of the information and thereby reducing both command/address bus and data bus bandwidth consumption. In one embodiment, a memory device comprises a memory; a mode register storing information corresponding to the memory; and circuitry configured to, in response to the information in the mode register being modified by the memory device, generate a notification to a connected host device.

公开(公告)号：US20240146525A1

公开(公告)日：2024-05-02

申请号：US18407963

申请日：2024-01-09

Applicant: Lodestar Licensing Group LLC

Inventor： Travis Duane Nelson ,  Lance W. Dover

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/40

CPC classification number: H04L9/088 ,  H04L9/3247 ,  H04L63/08

Abstract: A system, method and apparatus to control memory devices over computer networks. For example, a server system establishes a secure authenticated connection with a client computer system to receive a request having a batch identification that is configured in the server system to identify a batch of multiple memory devices. After determining that the client computer system is eligible to control the multiple memory devices in the batch, the server system transmits to the client computer system a response. The response contains control data for each respective memory device in the batch. The control data is based on at least a cryptographic key stored in the server system in association with the respective memory device. Using the control data the client computer system submits a command with a digital signature to the respective memory device, which validates the digital signature prior to execution of the command.

公开(公告)号：US11972152B2

公开(公告)日：2024-04-30

申请号：US18095878

申请日：2023-01-11

Applicant: Lodestar Licensing Group, LLC

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20240138146A1

公开(公告)日：2024-04-25

申请号：US18382863

申请日：2023-10-22

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H10B41/41 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C5/063 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240127867A1

公开(公告)日：2024-04-18

申请号：US18519212

申请日：2023-11-27

Applicant: Lodestar Licensing Group, LLC

Inventor： Matthew D. Rowley

IPC: G11C5/14 ,  G06F1/28 ,  G06F1/3296

CPC classification number: G11C5/148 ,  G06F1/28 ,  G06F1/3296 ,  G06F1/3203

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

公开(公告)号：US20240118968A1

公开(公告)日：2024-04-11

申请号：US18221176

申请日：2023-07-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Jonathan Scott Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1072 ,  G06F12/0246

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US20240118831A1

公开(公告)日：2024-04-11

申请号：US18206934

申请日：2023-06-07

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/068 ,  G11C16/0483 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US11947412B2

公开(公告)日：2024-04-02

申请号：US18094799

申请日：2023-01-09

Applicant: Lodestar Licensing Group LLC

Inventor： Dean D. Gans

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/16 ,  G11C11/22 ,  G11C29/04

CPC classification number: G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/1668 ,  G11C11/2257 ,  G11C11/2277 ,  G11C29/04

Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.